In short: A gate all around (GAA) nanosheet transistor wraps the gate electrode around all four sides of a stack of thin silicon channels, giving the gate near-total control over current. It is the device that replaces the FinFET at the 3nm and 2nm nodes, cutting leakage and letting designers tune drive strength by simply widening the sheets.
A gate all around transistor is a field-effect transistor whose gate material completely surrounds the conducting channel on every side. Instead of the channel being a slab sitting on the silicon surface (planar) or a thin vertical fin touched on three sides (FinFET), the channel in a GAA device is one or more horizontal silicon nanosheets threaded through the gate like beads on a string. Because the gate wraps the channel 360°, it can switch the transistor on and off far more decisively.
The industry's production form of GAA is the nanosheet FET (Samsung markets its variant as MBCFET, Intel as RibbonFET). A typical device stacks two to four silicon sheets, each only a few nanometers thick, vertically on top of one another. The gate stack — a high-k dielectric such as hafnium oxide plus a metal work-function layer — fills every gap between the sheets and encloses them.
The FinFET served the industry from roughly the 22nm node down to 5nm. But as gate lengths shrank toward 12–15nm, even a three-sided gate lost grip on the channel. Electrons began to leak through when the device was supposed to be off, a family of problems called short-channel effects: drain-induced barrier lowering, rising off-state current, and a degraded subthreshold slope that forced higher supply voltages.
FinFET drive current can only be increased in quantised steps — you add another whole fin, which jumps width by a fixed amount and costs area. There is no way to ask for "15% more drive." GAA solves both problems at once: full electrostatic control and continuously tunable width.
In the on state, a voltage on the gate inverts the surface of each silicon sheet and electrons flow from the source terminal, through all the stacked channels in parallel, to the drain. Because the sheets are stacked, the effective channel width is the sum of all sheet widths — so three wide sheets deliver roughly three times the current of one, in the same footprint.
The animation below traces carriers moving source-to-drain through a nanosheet while the gate field (shown pulsing) holds the channel open.
GAA fabrication starts with an epitaxial superlattice — alternating layers of silicon and silicon-germanium (SiGe) grown on the wafer. The silicon layers become the channels; the SiGe layers are sacrificial spacers. After the fin-like stack is patterned and the dummy gate defined, a selective etch removes only the SiGe, leaving the silicon sheets suspended like shelves. This step is called the channel release. The high-k dielectric and metal gate are then deposited everywhere, filling the gaps so the gate wraps each sheet.
The advantages are substantial:
The trade-offs are real too: channel release and inner-spacer formation add process complexity and cost, parasitic capacitance between the closely stacked sheets must be managed carefully, and self-heating rises because the sheets are thermally isolated from the substrate.
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Explore CourseTron Courses →Nanosheet FET is the mainstream implementation of the gate all around concept. GAA is the general class (any geometry where the gate fully surrounds the channel, including nanowires); the stacked horizontal nanosheet is the version foundries actually ship at 3nm and 2nm.
Samsung introduced GAA at its 3nm node, while TSMC stayed on FinFET for 3nm and moves to GAA nanosheets at 2nm. Intel adopts GAA (RibbonFET) at its 18A/20A generation. So the FinFET-to-GAA transition spans roughly the 3nm–2nm era.
More gate coverage means stronger control of the channel potential. That raises the energy barrier blocking leakage in the off state and sharpens switching, so the transistor turns off more completely and can operate at a lower, more power-efficient supply voltage.
The roadmap points to forksheet FETs (a dielectric wall letting n- and p-devices sit closer) and then CFET, which stacks the n-type device directly over the p-type to shrink the standard cell further. All of these build on the GAA channel-release process.
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