In short: A FinFET wraps its gate around three sides of a vertical silicon fin, but below roughly 5 nm the fin can no longer be made thin enough to stop leakage — so the industry moved to gate-all-around (GAA) nanosheets, where the gate surrounds the channel on all four sides and restores the electrostatic control that short channels demand.
For almost a decade the FinFET was the workhorse of advanced CMOS, from Intel's 22 nm "Tri-Gate" in 2012 through TSMC and Samsung's 16/14/7/5 nm nodes. Yet at the 3 nm/2 nm frontier the fin ran out of room. This article explains why gate control matters, how short-channel effects (SCE) scale, and the concrete device physics that pushed foundries toward gate-all-around nanosheets.
Why the gate has to "wrap" the channel
A MOSFET is a capacitor steering a resistor. The gate couples capacitively to the channel and raises or lowers the barrier that electrons must cross from source to drain. The problem is that the drain also couples to the channel. As the channel gets shorter, the drain's field starts lowering that same barrier — the device partly turns itself on. We call this drain-induced barrier lowering (DIBL), and it is the headline short-channel effect alongside threshold-voltage roll-off and degraded subthreshold slope.
The defence is simple to state: the gate must dominate the channel's electrostatics more strongly than the drain does. Engineers capture this with the natural length λ — roughly the distance the drain field penetrates into the channel. You want the physical gate length Lg to be several times λ. Crucially, λ shrinks as you give the gate more sides:
Key fact: For a double-gate/fin structure λ ≈ √(εsi/2εox·tsi·tox), while for a gate-all-around cylindrical/sheet channel the body term scales with the channel area enclosed, giving a smaller λ for the same thickness. In plain terms, surrounding the channel lets you keep a longer effective channel's electrostatics in a shorter footprint.
What the FinFET bought us — and where it stalled
The FinFET replaced a flat channel with a tall, thin fin and draped the gate over three sides. Making the fin thin (single-digit nanometres) is what kills DIBL, because a thin body leaves no neutral region for the drain field to grab. Intel's 22 nm Tri-Gate reported DIBL and subthreshold slope close to ideal, with far lower off-state leakage at the same drive current than the preceding 32 nm planar part.
But fins have an awkward property: drive strength comes in quanta. Current scales with fin height and the number of fins, so a designer gets 1, 2, or 3 fins per device — never 1.5. Making fins taller to add drive makes them mechanically fragile and raises parasitic capacitance. By 3 nm-class design rules the fin width needed to suppress SCE fell below what lithography and variability could reliably hold, and fin pitch scaling had stalled. The gate simply could not out-vote the drain any longer with only three sides.
Gate-all-around nanosheets: closing the fourth face
GAA stacks horizontal silicon sheets (or ribbons/wires) with the gate material filling the gaps so it wraps all four surfaces of every sheet. Samsung's 3 nm MBCFET and Intel's RibbonFET (20A/18A) are the production incarnations; TSMC adopts nanosheets at N2. The payoff is twofold:
- Electrostatics. A fully surrounded channel gives the lowest λ of any planar-compatible geometry, so you can scale Lg further while holding DIBL and subthreshold swing in check.
- Design flexibility. Drive current is set by sheet width, which is continuously tunable. A designer dials Weff by drawing a wider nanosheet instead of adding whole fins — a cleaner knob for standard-cell and analog sizing.
Side-by-side: the numbers that matter
| Metric | Planar | FinFET | GAA nanosheet |
|---|---|---|---|
| Gated channel faces | 1 | 3 | 4 |
| Subthreshold swing (typical) | >90 mV/dec | ~65–70 mV/dec | ~60–65 mV/dec |
| DIBL control | Poor | Good | Best |
| Drive-current granularity | Continuous (W) | Quantised (fins) | Continuous (sheet W) |
| Practical floor | ~28 nm | ~5 nm class | 2 nm and below |
Key fact: The ideal subthreshold swing at room temperature is ~60 mV/decade (the kT/q·ln10 Boltzmann limit). FinFETs got close; GAA squeezes nearer to it, which directly lowers the supply voltage you can run at for a given leakage budget — the real currency of power efficiency.
What this means in the EDA flow
These device changes ripple straight into the design tools. New transistor architectures ship as updated process design kits (PDKs) with GAA-aware SPICE models (BSIM-CMG covers both FinFET and GAA). In practice you characterise cells in Synopsys PrimeLib/HSPICE or Cadence Spectre against the foundry model, run parasitic extraction that now accounts for the wrap-around gate capacitance, and sign off timing and power in Synopsys PrimeTime. Physical verification (Siemens Calibre) enforces the nanosheet-specific DRC rules — sheet width quantisation windows, inner-spacer geometry, and the dielectric isolation between stacked sheets.
If you want hands-on exposure to how these models and sign-off flows behave on real nodes, our partner design house Avecas VLSI design services runs production tapeout flows that mirror exactly this toolchain.
Where it goes next: CFET and beyond
Nanosheets are not the end. The next lever is stacking an n-type sheet device directly over a p-type one — the complementary FET (CFET) — to shrink standard-cell height further. GAA is the enabling geometry for that vertical integration, because a surrounding gate is what makes each stacked device controllable in isolation. The through-line of the whole story is unchanged: every generation finds a new way to give the gate more authority over the channel than the drain has.
For the groundwork on how we got from flat transistors to fins, read our companion piece FinFET vs planar MOSFET, and for the electrostatics in depth see short-channel effects explained. You can also browse the full device-physics track on our courses page.
Ready to design on GAA nodes? Join CourseTron's Advanced CMOS Device & PD course and build a full nanosheet standard-cell flow, hands-on. Prefer instructor-led training? See ChipXpert VLSI training.
Frequently asked questions
Is a GAA nanosheet the same thing as a nanowire FET?
They are the same family — gate-all-around — but a nanowire has a narrow, roughly square cross-section while a nanosheet is a wide, thin ribbon. The sheet geometry wins in production because its width is a continuous drive-current knob, whereas narrow wires would need many parallel wires to hit the same current.
Why did FinFETs stop scaling around 3 nm?
To keep short-channel effects in check the fin body must be made ever thinner, but below a few nanometres the fin becomes too fragile and too variable to manufacture reliably, and fin pitch scaling had already stalled. With only three gated faces, the gate could no longer out-control the drain field at those channel lengths.
Does GAA reduce power consumption?
Indirectly but significantly. Better electrostatics push the subthreshold swing closer to the 60 mV/decade limit and suppress DIBL, which lets the chip run at a lower supply voltage for the same leakage. Since dynamic power scales with the square of voltage, that is a large efficiency gain.
Do I need new EDA tools for GAA designs?
Not new tools, but new model and rule decks. The same Synopsys, Cadence and Siemens flows apply; you consume a GAA-enabled PDK with BSIM-CMG SPICE models, wrap-around-aware parasitic extraction, and nanosheet-specific DRC rules.