DRAM storage capacitors

In short: A DRAM cell stores one bit as charge on a tiny capacitor; to keep ~20-30 fF of capacitance while the cell footprint shrinks below 20 nm, makers either dig a deep trench into the silicon or stack a tall crown/pillar above it, both relying on extreme high-aspect-ratio etch and thin high-k dielectrics, and the cell must be refreshed every ~64 ms because that charge leaks away.

Every modern computer's main memory rests on one of the most physically demanding structures in all of semiconductor manufacturing: the DRAM storage capacitor. A dynamic RAM cell is deceptively simple on paper, 1 transistor plus 1 capacitor (the "1T1C" cell), yet keeping that capacitor functional as the cell pitch marches from 30 nm toward 10 nm has driven some of the most aggressive process engineering in the industry. This article walks through why the capacitor exists, the trench-versus-stacked design split, the high-aspect-ratio (HAR) etch that makes it buildable, and the retention and refresh physics that govern how often the data must be rewritten.

Why a capacitor at all?

SRAM stores a bit in a cross-coupled latch (6 transistors) that holds its state as long as power is applied. DRAM trades that for density: a single access transistor gates charge onto a capacitor. Charge present above a threshold reads as a logic "1"; an empty cell reads "0". With one transistor and one capacitor per bit, DRAM reaches cell areas around 6F² (F = half the minimum pitch), which is why your phone has gigabytes of DRAM but only kilobytes-to-megabytes of on-die SRAM cache.

The catch is the sense margin. A sense amplifier must detect the charge sharing between the cell capacitor (C_s) and the much larger bit-line capacitance (C_BL, often 100-300 fF). The voltage swing seen at the sense amp is roughly ΔV = V_cell × C_s / (C_s + C_BL). To keep ΔV above ~100 mV, designers have held C_s near a stubborn 25 fF per cell for three decades, even as the area available to build that capacitor has collapsed by orders of magnitude.

Key fact: Despite cell areas shrinking by more than 100× since the 1990s, the target storage capacitance has stayed pinned near 20-30 fF. Holding capacitance while area shrinks is the entire story of DRAM capacitor engineering.

The two architectures: trench vs. stacked

Because C = ε·A/d, keeping capacitance up as the top-down footprint shrinks means you must either grow the plate area vertically or raise the dielectric constant ε. Two families emerged to win area in the third dimension.

Trench capacitor

The trench approach, long championed by IBM/Qimonda and in some embedded DRAM, etches a deep narrow hole straight into the silicon substrate. The capacitor lives below the transistor, so the cell's surface stays flat, which simplifies the back-end interconnect and metallization. A trench 7-8 µm deep at a sub-100 nm opening reaches aspect ratios in the 60:1 to 80:1 range. The upside is a planar top surface; the downside is that etching and uniformly lining such deep holes in crystalline silicon is brutal, and trench DRAM largely lost the mainstream commodity race.

Stacked capacitor

Samsung, SK hynix, and Micron settled on the stacked capacitor, built above the transistor in the back end as a tall hollow cylinder (a "crown" or "one-cylinder-stack") or solid pillar. Modern stacked capacitors stand roughly 1.5-2 µm tall over an opening of 30-40 nm, giving aspect ratios well past 50:1 and now approaching 100:1 at the leading edge. The tall skinny structures are mechanically fragile, so support "mesh" lattices tie neighboring cylinders together so they don't topple during wet processing.

High-aspect-ratio etch: the enabling (and limiting) step

Whether you dig down or build up, the defining process is the HAR etch that forms the hole. A deep contact or capacitor hole at 60:1 is etched in oxide/nitride stacks or silicon using fluorocarbon or Bosch-style plasma chemistries, and the challenge is keeping the profile vertical from top to bottom. Real failures include bowing (the mid-depth sidewall bulging outward), tapering (the bottom pinching shut), twisting, and incomplete etch. A single stuck etch at the bottom of one hole kills a cell.

Engineers model these etches with tools such as Synopsys Sentaurus and Lam/Coventor SEMulator3D process emulation, and verify the printed patterns upstream with optical proximity correction and Calibre (Siemens EDA) lithography checks. After the hole is open, a thin conformal electrode and dielectric must coat every square nanometer of the sidewall, which is the job of atomic layer deposition (ALD): self-limiting, one-monolayer-per-cycle growth is the only way to line an 80:1 hole uniformly.

Key fact: The dielectric itself has gone from silicon dioxide (ε≈3.9) to high-k films, ZrO₂/Al₂O₃/ZrO₂ "ZAZ" and then ferroelectric-adjacent HfO₂-based stacks, pushing effective ε above 40 so a few-nanometer film delivers the needed 25 fF.

Retention and refresh: why DRAM is "dynamic"

The stored charge does not stay put. Junction leakage through the access transistor, gate-induced drain leakage, and especially sub-threshold leakage all bleed charge off the capacitor. Once the cell voltage droops below the sense-amp decision point, the bit is lost. DRAM therefore reads and rewrites (refreshes) every cell on a fixed cadence, the retention time, standardized by JEDEC at 64 ms at normal temperatures (dropping to 32 ms above 85 °C because leakage roughly doubles every ~10 °C).

Refresh is not free. In a 16 Gb device the memory controller must cycle through tens of thousands of rows every 64 ms, and those cycles steal bandwidth and burn power, the reason LPDDR introduces temperature-compensated and partial-array self-refresh. Retention also has a long, ugly tail: a handful of "weak" cells leak far faster than the population average, and variable retention time (VRT) cells randomly switch between good and bad states. DRAM makers screen these with long soak tests and repair them using redundant rows and on-die ECC.

Retention weakness is also the root of the row hammer security problem: rapidly toggling one row accelerates charge loss in physically adjacent rows, flipping their bits before the next scheduled refresh. Mitigations such as targeted refresh and the DDR5 Refresh Management (RFM) command exist precisely because the capacitor's charge is so marginal.

Where it is heading

Planar capacitor scaling is near its physical cliff, you cannot keep making holes taller and thinner forever without them collapsing. The industry's answer is to go fully vertical, much as NAND did: 4F² vertical-channel-transistor DRAM and eventually stacked 3D DRAM, where capacitors lie horizontally in a stack of decks. These revive ideas from both camps, high-k ALD dielectrics from the stacked era and buried structures reminiscent of trench, and keep the same iron rule: deliver ~20 fF of reliable, slowly-leaking charge in an ever smaller box.

If you want to go deeper on how the cell array, sense amplifiers, and back-end integration tie together, see our companion pieces on DRAM fabrication and high-aspect-ratio plasma etch. Hands-on process modeling and TCAD skills are covered in the CourseTron course catalog, and for industry-grade physical design and verification mentoring our design-services partner Avecas VLSI design services works on real tape-out flows.

Ready to master memory process technology from etch to sense amp? Explore CourseTron's Nano Fabrication track and build the TCAD and device-physics fluency that interviewers at every memory fab look for. Browse the Nano Fab courses →

Frequently asked questions

Why does DRAM need to be refreshed but SRAM does not?

SRAM holds its bit in a powered feedback latch that actively restores its own state, so it stays valid as long as power is on. DRAM stores the bit as passive charge on a capacitor that leaks through the transistor and junctions, so the data must be read and rewritten, refreshed, every ~64 ms before the charge droops below the sense amplifier's threshold.

What is the difference between a trench and a stacked capacitor?

A trench capacitor is etched down into the silicon substrate below the transistor, giving a flat top surface. A stacked capacitor is built up above the transistor as a tall crown or pillar. Both gain plate area vertically, but stacked capacitors dominate commodity DRAM while trench designs are now mostly niche or embedded.

Why is a high aspect ratio so hard to manufacture?

Etching a hole 50-100 times deeper than it is wide invites profile defects, bowing, tapering, twisting, and incomplete etch, and then every sidewall must be coated conformally with electrode and dielectric. Only self-limiting atomic layer deposition can line such deep holes uniformly, and a single failed hole kills a bit cell.

How much capacitance does one DRAM cell actually store?

Industry has held storage capacitance near 20-30 fF (commonly cited as ~25 fF) for decades, because the sense amplifier needs a roughly 100 mV swing against a much larger bit-line capacitance. Holding that value as cell area shrinks is what forces taller structures and higher-k dielectrics.