In short: Multiple patterning splits one dense layout into several coarser masks (LELE) or uses self-aligned spacers (SADP/SAQP) so a 193 nm immersion scanner — physically limited to roughly an 80 nm half-pitch — can still print the ~20–40 nm pitches that 10 nm, 7 nm and 5 nm logic demand.
When an optical lithography tool hits its resolution wall, the industry does not simply stop shrinking. For roughly a decade — from the 20 nm node until EUV production ramped — every leading-edge chip was built by printing the same critical layer two, three, or four times. This article explains the two families that made that possible: litho-etch litho-etch (LELE) pitch splitting and self-aligned double and quadruple patterning (SADP/SAQP), why one is chosen over the other, and the design and verification burden each imposes.
The wall: why one exposure is not enough
Printable half-pitch is bounded by the Rayleigh criterion, CD = k₁·λ/NA. A 193 nm immersion scanner (ArF, water immersion) has NA ≈ 1.35 and a practical single-exposure k₁ floor near 0.28. That puts the smallest reliable half-pitch around 40 nm — a minimum pitch of about 80 nm. But a 7 nm FinFET fin pitch is ~30 nm and its tightest metal (M1/M2) pitch is ~40 nm. The scanner physically cannot resolve those lines in one shot; the aerial image contrast collapses and the lines merge.
? 193i immersion tops out near an 80 nm pitch. A 7 nm node needs ~40 nm metal pitch. You are a factor of two short — which is exactly why "double" patterning exists.
LELE: color the layout, print it twice
Litho-Etch-Litho-Etch takes a single dense layer and decomposes it into two masks. Features too close to print together are assigned to different masks ("colors"), each mask is printed and etched into a hard mask separately, and the two patterns are merged into the final layer. Each individual mask now sees only ~80 nm pitch — comfortably within the scanner's reach.
The catch is overlay. Mask B must land within a few nanometers of Mask A, and any misalignment shows up directly as line-edge placement error and variable spacing between A- and B-colored lines. This asymmetry — A-to-A spacing is lithographically tight but A-to-B spacing floats with overlay — is why LELE layers carry extra parasitic-RC variation. Extending the idea to LELELE (triple) and LELELELE (quadruple) multiplies cost and overlay stack-up fast, so pure LE is rarely pushed past three colors.
Coloring conflicts and the odd-cycle problem
Two-coloring a layout is a graph problem: nodes are polygons, an edge joins any two that are closer than the single-exposure limit, and you must 2-color the graph so no edge connects same-colored nodes. A layout containing an odd cycle (three mutually too-close features, for instance) is not 2-colorable — a native coloring conflict that no decomposer can resolve. The fix is either a layout change or a stitch, where one polygon is cut and shared across both masks at an overlap. EDA sign-off tools (Siemens Calibre Multi-Patterning, Synopsys IC Validator, Cadence Pegasus) flag these conflicts during DRC and feed them back to the designer. That is why multi-patterning design rules are not just "min spacing" numbers but coloring-aware constraints.
SADP: let the sidewall define the pitch
Self-Aligned Double Patterning sidesteps overlay almost entirely. You print a relaxed-pitch "mandrel," deposit a conformal spacer film (ALD, e.g. 15 nm of oxide or nitride) over it, anisotropically etch so material survives only on the vertical sidewalls, then strip the mandrel. Every mandrel leaves two spacer lines, so the final line pitch is set by the deposited film thickness — an atomic-layer-controlled dimension — rather than by the scanner or by mask-to-mask overlay.
? In SADP the critical dimension is the ALD spacer thickness (±~0.5 nm control), not an optical exposure. That is why spacer flows dominate fin and fin-pitch formation at 16/14 nm and below.
SADP's price is topology: spacers form as closed loops around each mandrel, so you always need a second "cut" or "block" mask to trim the loop ends and define where lines actually terminate. SADP is therefore ideal for highly regular, unidirectional arrays — FinFET fins, dense 1-D metal grids — and awkward for arbitrary 2-D routing. SAQP simply repeats the spacer step: mandrel → spacer → the first spacer becomes the mandrel for a second spacer → final pitch quartered. Intel and foundry 7 nm/5 nm fin and lower-metal layers lean heavily on SAQP.
LELE vs. SADP/SAQP at a glance
| Attribute | LELE / LE³ | SADP / SAQP |
|---|---|---|
| Pitch division | 2× (3× for LE³) | 2× (4× for SAQP) |
| CD set by | Litho + overlay | ALD spacer thickness |
| Overlay sensitivity | High (A-to-B spacing floats) | Low (self-aligned) |
| Best for | 2-D, flexible routing | 1-D regular arrays, fins |
| Extra masks | 1 per added color | 1 cut/block mask |
| Main design burden | Coloring/odd-cycle DRC | Cut placement, line-end control |
What this means for the physical designer
Multiple patterning pushed design rules from simple geometry toward restrictive, grid-based layout. Tight layers become effectively unidirectional; routers in Synopsys IC Compiler II and Cadence Innovus must respect color assignment so that adjacent tracks land on alternating masks; and sign-off runs a color-correctness check alongside classic DRC. Even with EUV now handling the single tightest layers, many intermediate layers at 5 nm and 3 nm still use 193i multi-patterning because it is cheaper per wafer than a second EUV pass. Teams building that intuition in a structured flow — or evaluating it against a real tapeout — often lean on specialized training such as ChipXpert's VLSI programs to connect the lithography physics to the EDA rule decks.
For the broader optical picture — immersion limits, the NA story, and the move to 13.5 nm light — see our companion piece on EUV lithography, and for how these patterned layers get verified, our write-up on design rule checking and multi-patterning DRC.
Want to go from "I've heard of SAQP" to actually two-coloring a layout and reading a multi-patterning rule deck? Explore the Nano Fab track in CourseTron's course catalog.
FAQ
Why not just use EUV and skip multiple patterning entirely?
EUV single-exposure handles the tightest layer, but EUV throughput, mask, and tool cost are high. For many mid-tier layers, a 193i double-patterning pass is cheaper per wafer, so modern nodes mix both. EUV itself needs double patterning below roughly 30 nm pitch.
What is the difference between SADP and SAQP?
SADP (self-aligned double) halves pitch with one spacer step; SAQP (self-aligned quadruple) runs the spacer process twice — the first spacers become mandrels for a second spacer — quartering the original mandrel pitch.
What is an "odd cycle" in multi-patterning?
It is a set of features whose too-close relationships form a loop of odd length in the conflict graph, making the layer impossible to 2-color. It must be fixed by editing the layout or by stitching a polygon across both masks.
Which EDA tools handle multi-patterning decomposition?
Siemens Calibre Multi-Patterning, Synopsys IC Validator, and Cadence Pegasus/Innovus perform color decomposition and coloring-aware DRC during physical design and sign-off.