In short: Backside power delivery (BSPDN) moves the power distribution network from the crowded frontside metal stack to the back of the thinned wafer, freeing routing tracks for signals and cutting IR-drop by roughly half at the 2 nm node and below.
For three decades, every wire on a chip — power and signal alike — lived on one side of the silicon. As transistors shrank past the 3 nm node, that single-sided arrangement became the bottleneck. Backside power delivery network (BSPDN) is the architectural answer: split the two jobs onto two faces of the wafer. This article explains why it is happening now, how the process actually works, and what it changes for anyone doing physical design or sign-off.
Why frontside power ran out of room
On a conventional chip, external power enters through C4 bumps at the top of the metal stack and travels down through a dozen or more interconnect layers (M0 up to the redistribution layer) before reaching the transistor source/drain rails at the bottom. The signal nets also compete for those same layers. The result is a tug-of-war: wide, thick metal is needed for low-resistance power straps, but every micron of track spent on a power rail is a track denied to signal routing.
At advanced nodes the power grid was consuming 15–20% of the lower-level routing resources, and the long vertical path from bump to device accumulated significant parasitic resistance. That resistance shows up as IR-drop — the local supply voltage sags below the nominal VDD — which eats into timing margin and forces designers to over-design clock and critical paths.
Key fact: Intel's PowerVia test vehicle reported more than a 30% reduction in platform IR-drop and roughly a 6% frequency gain, simply by moving the power delivery to the backside — no transistor change required.
The buried power rail: the enabling step
BSPDN does not start with the backside — it starts by burying the standard-cell power rails inside the silicon, below the transistors. A buried power rail (BPR) is a deep trench (tungsten or ruthenium) etched into the substrate and the local interconnect, connecting VDD and VSS to the cell without occupying the M0/M1 tracks above. Because the rail is no longer on the frontside, standard cells can shrink in height — a 6-track cell can drop toward 5 tracks — which is itself a density win independent of the backside metal.
Once the rail is buried, the wafer is flipped, bonded to a carrier, and the bulk silicon is thinned from hundreds of microns down to a few hundred nanometers. Nano-through-silicon vias (nano-TSVs) are then drilled from the exposed backside to land on the buried rails, and a fresh backside metal stack (typically two to four thick layers) distributes power across the die.
Two flavors: PowerVia-style vs. direct backside contact
| Approach | How power reaches the device | Trade-off |
|---|---|---|
| Nano-TSV to buried rail (Intel PowerVia) | Backside metal → nano-TSV → buried rail → cell | Lower process risk; rail still consumes some device-layer area |
| Direct backside contact (imec BSCON / future nodes) | Backside metal contacts the transistor source/drain directly | Best area and resistance; tighter overlay and thermal demands |
Key fact: Moving power to the backside typically returns 10–20% of frontside routing resources to the signal network, which improves routability and can shorten average wirelength on congested blocks.
The IR-drop payoff, quantified
IR-drop scales with the resistance of the delivery path and the current drawn. Backside metal can be made far thicker and wider than the choked lower frontside layers, so its sheet resistance is dramatically lower. Combined with the shorter vertical distance, the end-to-end power-path resistance falls sharply. In practice design teams see static IR-drop budgets that were 40–50 mV on a frontside grid shrink toward 20–25 mV on an equivalent backside grid at the same current density — margin that can be reinvested in frequency or recovered as lower VDD for power savings.
New problems BSPDN creates
- Thermal. The backside metal now sits between the heat-generating transistors and the heat-sink/package on legacy flows. Removing the bulk silicon that used to spread heat means the thermal path must be re-engineered; junction temperatures can rise if the backside stack is not designed as a heat conductor too.
- Wafer handling. Thinning silicon to sub-micron thickness and bonding to a carrier wafer adds yield-critical steps. Overlay accuracy between frontside devices and backside vias is a hard lithography constraint.
- Design-tool and PDK readiness. Place-and-route, extraction and sign-off must model two metal stacks and the nano-TSVs. Cadence Innovus and Synopsys IC Compiler II have added backside-aware power planning, while Siemens Calibre and Synopsys StarRC handle backside parasitic extraction and backside DRC rule decks.
If you are coming to this from device physics, it pairs naturally with the material-stack changes in high-k metal gate technology, and on the interconnect side with the scaling pressures discussed in EUV lithography basics. Teams building production flows for these nodes often lean on dedicated physical design and sign-off services to de-risk the backside extraction and thermal closure steps.
Where it ships
Intel introduced PowerVia on its 18A-class process as the industry's first high-volume BSPDN, and TSMC and Samsung have roadmaps bringing backside power to their 2 nm-generation nodes. The combination of gate-all-around (GAA) nanosheet transistors with BSPDN is widely treated as the defining pair for the sub-2 nm era: GAA fixes electrostatic control, BSPDN fixes power delivery and routability at the same time.
FAQ
Is BSPDN the same as a through-silicon via in 3D stacking?
No. Classic TSVs in 3D-IC stacking are large (micron-scale) vias connecting separate stacked dies. BSPDN uses nano-scale TSVs within a single thinned die purely to route power from its own backside to its own transistors.
Does backside power improve performance or just density?
Both. Freeing frontside tracks improves routability and density, while the lower-resistance power path reduces IR-drop, which recovers timing margin that can be spent on higher frequency or lower voltage.
Why is thermal management harder with BSPDN?
The wafer is thinned to remove the bulk silicon that previously helped spread heat, and metal is placed on the backside. The backside stack and package must therefore be co-designed to conduct heat out, or junction temperatures rise.
Do I need new EDA tools for a backside-power design?
You need backside-aware versions of your existing flow: power planning that understands two metal stacks, extraction (StarRC/Calibre) that models nano-TSVs and backside parasitics, and DRC decks for the backside layers. Major vendors already support these in recent releases.
Want to design and sign off real backside-power and GAA blocks hands-on? Our CourseTron Nano Fab track walks you through buried rails, nano-TSV extraction and IR-drop closure on industry tools. For focused VLSI upskilling, see our training partner ChipXpert.