In short: Atomic layer deposition grows films one self-limiting monolayer at a time by alternating two gas pulses that each saturate the surface, giving sub-nanometre thickness control and near-perfect conformality — which is exactly why it deposits the high-k gate dielectrics (HfO₂) and metal liners inside today's 3D transistors.
When a MOSFET gate oxide is only a handful of atoms thick and must coat the vertical walls of a FinFET or the stacked channels of a gate-all-around device, ordinary deposition fails: it is too fast, too uneven, and impossible to stop at the right angstrom. Atomic layer deposition (ALD) solves this by trading speed for exquisite control. It is the enabling process behind the high-k/metal-gate stack that replaced silicon dioxide at the 45 nm node and the only practical way to line a trench with a 90:1 aspect ratio.
The self-limiting idea
ALD is a special case of chemical vapor deposition (CVD) in which the reaction is deliberately split into two half-reactions that never happen at the same time. Each precursor is pulsed in separately, reacts only with surface sites, and stops once those sites are consumed. Because the gas cannot react with itself, the growth per cycle is fixed by surface chemistry, not by how much gas you dose or for how long. This saturating, self-terminating behaviour is the whole trick.
The textbook example is HfO₂ from tetrakis(dimethylamido)hafnium (TDMAH) and water:
- Pulse A: TDMAH reacts with surface –OH groups, leaving Hf–N(CH₃)₂ ligands anchored to the surface. Once every hydroxyl is used, the reaction halts.
- Purge: inert N₂ or Ar sweeps away excess precursor and byproducts.
- Pulse B: H₂O reacts with the dangling ligands, converting them to Hf–OH and regenerating the hydroxyl surface for the next cycle.
- Purge: again clear the chamber.
One A–purge–B–purge sequence is one cycle, and it adds a fixed growth per cycle (GPC) — typically 0.09–0.11 nm for HfO₂, roughly one third of a unit cell. Want a 2 nm gate dielectric? Run about 20 cycles. The thickness is literally counted out.
Key fact: Because each half-reaction saturates, a 10% error in precursor dose produces essentially zero error in deposited thickness — the opposite of CVD, where flux directly controls rate.
Why conformality is "free"
In CVD or PVD, the first surfaces a precursor reaches get coated fastest, so deep trenches starve and sidewalls thin out. In ALD the surface reaction only proceeds where sites are available, and precursor molecules keep diffusing into the trench during a long enough pulse until every site — top, sidewall, and bottom — is reacted. The result is step coverage that routinely exceeds 95% even at aspect ratios above 40:1.
This is the property that makes ALD indispensable for 3D structures: the gate dielectric wrapping a FinFET fin, the TiN work-function metal inside a GAA nanosheet stack, the W-nucleation layer and Al₂O₃ moisture barrier in DRAM capacitors, and the spacer-defined patterns in self-aligned double patterning (SADP).
The high-k gate dielectric motivation
By the 90 nm node, SiO₂ gate oxides had shrunk to ~1.2 nm — about five atomic layers — and gate leakage from direct tunnelling was exploding to amps per cm². The fix was a physically thicker film with a higher dielectric constant k, so capacitance is preserved while the tunnelling distance grows. Hafnium-based oxides (k ≈ 20–25 versus 3.9 for SiO₂) let a 3 nm HfO₂ layer deliver the same capacitance as a 0.5 nm SiO₂ equivalent oxide thickness (EOT) while cutting leakage by two to three orders of magnitude.
| Material | k (dielectric const.) | Typical role |
|---|---|---|
| SiO₂ | 3.9 | Legacy gate oxide / interfacial layer |
| Al₂O₃ | ~9 | Barrier, DRAM, passivation |
| HfO₂ | ~20–25 | High-k gate dielectric (45 nm onward) |
| ZrO₂ | ~25–40 | DRAM capacitor dielectric |
Key fact: Replacing SiO₂ with ALD-grown HfO₂ at 45 nm was one half of Intel's "high-k/metal gate" transition; the other half was depositing TiN/TiAl work-function metals — also by ALD — to set the right threshold voltage for NMOS and PMOS.
For a device engineer, the dielectric is only useful if the tools model it correctly. The high-k layer and its ~0.5 nm SiO₂ interfacial layer are captured in the TCAD and SPICE flows — Synopsys Sentaurus process simulation and BSIM-CMG compact models include high-k/metal-gate parameters so that EOT, gate leakage, and C–V behaviour can be predicted before silicon.
Thermal vs. plasma-enhanced ALD
Thermal ALD relies purely on heat (often 150–350 °C) to drive the surface reactions and is the gentlest, most conformal variant. Plasma-enhanced ALD (PEALD) replaces the co-reactant with radicals (O*, N*, H*) generated in a plasma, which lets you deposit at lower temperature, get denser films, and reach materials like TiN and TaN that thermal chemistry struggles with. The trade-off: radicals recombine on long trench walls, so PEALD conformality in very high-aspect-ratio features is usually worse than thermal ALD.
Practical limits and gotchas
- Throughput: at ~0.1 nm/cycle and seconds per cycle, ALD is slow. A 5 nm film is hundreds of cycles. Spatial ALD and batch tools amortise this.
- Nucleation delay: on inert starting surfaces (e.g. H-terminated Si or metals) the first several cycles may not grow at all until enough reactive sites appear — important when you need an abrupt interface.
- Temperature window: too cold and precursor condenses or doesn't react; too hot and it decomposes (CVD-like, non-self-limiting) or desorbs. True ALD only exists inside the flat "ALD window".
- Impurities: incomplete purging or low temperature leaves carbon and hydrogen in the film, degrading k and leakage.
ALD sits alongside its deposition cousins — see our primer on CVD, PVD and ALD compared for where each wins, and the high-k/metal-gate stack for how these films assemble into a working transistor. For hands-on process and device modelling, the training at ChipXpert's VLSI programs walks through the TCAD side end to end.
Go deeper: CourseTron's Nano Fabrication track covers ALD, high-k integration, and TCAD process modelling with worked examples and simulator labs. Explore the Nano Fab course →
Frequently asked questions
How is ALD different from CVD?
CVD exposes the surface to all reactants simultaneously, so growth rate depends on gas flux and is hard to stop precisely. ALD separates the reactants into alternating, self-limiting pulses, so each cycle adds a fixed sub-monolayer regardless of dose — giving angstrom thickness control and far better conformality at the cost of speed.
What does "growth per cycle" mean?
GPC is the film thickness added by one complete ALD cycle (two half-reactions plus purges). For HfO₂ it is around 0.1 nm. Total thickness is simply GPC times the number of cycles, which is why ALD thickness is set by counting cycles.
Why is HfO₂ used for gate dielectrics instead of SiO₂?
Its dielectric constant (~20–25) is roughly five times that of SiO₂, so a physically thicker HfO₂ film gives the same capacitance while dramatically reducing quantum-tunnelling gate leakage — essential once SiO₂ reached ~1 nm.
Can ALD coat deep trenches evenly?
Yes. Because the reaction only proceeds on available surface sites and precursor keeps diffusing in during the pulse, ALD achieves greater than 95% step coverage even in features with aspect ratios above 40:1, which CVD and PVD cannot match.