In short: Planar NAND hit a physical wall near the 15 nm node because cells became too small to hold enough electrons reliably, so the industry rotated the bit line vertical and now stacks hundreds of charge-trap cells in a single etched pillar, scaling by layer count instead of lithography.
For roughly three decades, flash density grew the same way logic did: shrink the cell, pack more bits per square millimetre. Around 2013 that strategy collapsed for NAND. The answer was not a better lithography tool but a change of axis entirely. This article explains why planar NAND ended, how 3D NAND physically stacks cells into vertical strings, and why the charge-trap transistor replaced the floating gate in the process.
Why planar NAND ran out of road
A floating-gate flash cell stores a bit as electrons trapped on a conductive polysilicon island between the control gate and the channel. Read the threshold voltage, and the charge count tells you the stored value. The problem is simple arithmetic: as the cell shrinks, the floating gate holds fewer electrons. At the 15–16 nm planar node, a single cell stored on the order of only a few hundred electrons, and losing a dozen to leakage or read disturb could flip a bit.
Two effects made this fatal. First, cell-to-cell interference: adjacent floating gates are conductors, and their fringing fields shift a neighbour's apparent threshold as spacing drops below ~20 nm. Second, patterning cost: pushing planar NAND finer required multi-patterning immersion lithography, which multiplied mask steps and cost per wafer while delivering diminishing density. The economics inverted — each shrink cost more and bought less.
Key fact: A planar 15 nm MLC cell stored only a few hundred electrons per level. Modern 3D NAND relaxes the cell back to a far larger body, so each programmed state again spans a comfortable electron count — reliability returns even as areal density climbs.
The vertical idea: stack, don't shrink
3D NAND keeps the in-plane feature size deliberately loose (often 40–50 nm half-pitch) and instead grows density upward. Manufacturers deposit an alternating stack of insulator and either sacrificial nitride or conductive layers — 32, 64, 96, 176, 232, and now 300-plus pairs — then etch vertical holes straight down through the entire stack. Each hole becomes one NAND string: a column of series-connected cells sharing a single polysilicon channel.
Each horizontal conductive layer the pillar passes through acts as the word line (control gate) of one cell. Cells in the same pillar are electrically in series, source-to-drain, exactly like a classic NAND string — only now the "string" runs vertically. A 232-layer device therefore places ~232 cells in the footprint that planar NAND used for one.
Charge trap replaces the floating gate
You cannot easily wrap a conductive floating-gate island around every layer of a deep vertical hole. 3D NAND instead uses a charge-trap structure (SONOS-like): the pillar wall is lined, from channel outward, with a tunnel oxide, a silicon-nitride trapping layer, and a blocking oxide, with the word-line metal/polysilicon as the gate. Electrons are stored in discrete deep traps within the insulating nitride rather than on a conductor.
This matters for two reasons. An insulator does not conduct charge laterally, so a single pinhole defect leaks only locally instead of draining the whole store — intrinsically more robust. And because the trapping film is insulating, neighbouring cells no longer couple through a conductive gate, sharply cutting the cell-to-cell interference that killed planar scaling.
| Attribute | Planar floating gate | 3D charge trap |
|---|---|---|
| Scaling axis | Lithographic shrink (X–Y) | Layer count (Z) |
| Storage medium | Conductive poly island | Insulating nitride traps |
| Half-pitch (typical) | ~15 nm | ~45 nm (relaxed) |
| Dominant limiter | Electron count, interference | Etch aspect ratio, uniformity |
| Interference | Severe below 20 nm | Largely eliminated |
Programming and reading a vertical string
To program one cell, the stack biases that cell's word line high (Fowler–Nordheim tunnelling injects electrons into the nitride) while pass voltages keep every other transistor in the string fully on so the channel is conductive up to the target. Reading applies a sweep voltage to the selected word line and pass voltages to the rest, then senses whether the string conducts. Because density now relies on storing multiple bits per cell — TLC (3 bits, 8 levels) and QLC (4 bits, 16 levels) — the sense margins between threshold states are tiny, which is why controllers lean heavily on LDPC error correction and read-retry.
The new limiter: the high-aspect-ratio etch
Stacking does not make physics free — it relocates the hard problem. The dominant challenge is etching a hole with an aspect ratio exceeding 60:1 that stays perfectly vertical and the same diameter top to bottom through hundreds of layers. Any taper changes each cell's geometry with depth, spreading threshold distributions. This is why vendors adopt string stacking (etching two or more decks and bonding them) once a single etch becomes impractical, and why process-simulation and TCAD tools from the likes of Synopsys (Sentaurus), Siemens EDA, and Cadence are central to co-optimising the etch profile, deposition, and resulting device electrostatics before silicon.
Key fact: Modern 3D NAND channel holes exceed a 60:1 aspect ratio — comparable to drilling a 6-metre shaft 10 cm wide and keeping the walls straight. Etch uniformity, not lithography, now sets the scaling ceiling.
If you want to see how the front-end process steps — deposition, the channel etch, gate replacement, and contact formation — physically build these stacks, our companion guide on NAND flash fabrication walks the full flow. For how controllers manage wear and errors across these dense cells, see flash controller wear-leveling.
Want to design and characterise memory cells, not just read about them? CourseTron's Nano Fabrication and Device Physics track builds this from transistor fundamentals to 3D integration. Explore the full course catalogue.
Where this is heading
Layer counts keep climbing past 300, and the industry is pairing cell arrays with CMOS-under-array and wafer-bonded peripheral logic to push effective density further. The trade-off is always the same triangle: more layers raise capacity but strain etch uniformity, retention, and per-bit performance. For teams building the devices or the surrounding controllers, hands-on device and process training matters — our sister training brand ChipXpert's VLSI programs cover the fabrication and reliability side in depth.
Frequently asked questions
Is 3D NAND the same as SSD?
No. 3D NAND is the memory technology — the vertically stacked flash cells. An SSD is a product that combines many 3D NAND dies with a controller, DRAM cache, and firmware. Nearly all modern SSDs use 3D NAND, but the two terms describe different layers of the stack.
Why does 3D NAND use charge trap instead of floating gate?
A conductive floating gate is hard to wrap around every layer of a deep etched pillar and couples strongly to neighbours. The insulating nitride trap layer deposits conformally on the pillar wall, confines a defect's charge loss locally, and eliminates most cell-to-cell interference — making tall vertical strings reliable.
Does adding more layers reduce reliability?
More layers mainly stress the manufacturing etch rather than the physics of an individual cell. The real reliability pressure comes from storing more bits per cell (TLC, QLC), which shrinks sense margins; vendors offset this with stronger LDPC error correction, read-retry, and careful threshold placement.
Can planar NAND still be cheaper for small capacities?
For very small, low-cost parts planar NAND survived in niches, but its cost-per-bit stopped improving, so essentially all mainstream capacity scaling has moved to 3D. Economically, the vertical approach now wins at almost every capacity point that matters.