Post-Silicon

Test escapes and DPPM

By CourseTron Team ·  2 min read ·  Updated Oct 2026 💬 𝕏 in f
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    In short: A test escape is a defective die that passes the test program and ships anyway; DPPM counts those escapes per million shipped units, and driving it toward single digits means closing coverage gaps and screening marginal "walking wounded" parts with statistical outlier methods, not just adding more vectors.

    Every chip that reaches a customer board has passed your test program. The uncomfortable truth of post-silicon is that "passed the tests" and "is actually good" are not the same statement. The gap between them is measured in test escapes, and the industry currency for that gap is DPPM — defective parts per million. For an automotive or datacenter customer, a DPPM number is contractual: miss it and you own the field returns, the 8D reports, and sometimes the recall.

    What exactly is a test escape?

    A test escape is a physically defective device that your manufacturing test flow classified as good. The defect was always there — a resistive via, a gate-oxide pinhole, a bridging particle — but the test program never created the electrical condition that exposes it. Escapes come from three recurring sources:

    • Coverage holes: a fault the pattern set simply does not sensitize. If your stuck-at ATPG coverage is 98.5%, roughly 1.5% of modeled faults are untested; some of those correspond to real silicon defects.
    • Wrong fault model: stuck-at patterns catch gross opens and shorts but miss timing-dependent and resistive defects that only a transition-delay or small-delay-defect (SDD) pattern would trip.
    • Marginal parts ("walking wounded"): a die that barely passes every limit — slightly leaky, slightly slow — and then drifts out of spec under field voltage, temperature, or aging.

    Rule of thumb: a 1% gap in defect coverage on a product with a 2% true defect density can translate to roughly 200 DPPM of escapes. Automotive AEC-Q100 programs typically target <1 DPPM, so the last decade of coverage improvement is where all the engineering happens.

    Where a defective die can end up Wafer / die pool Test program ATPG + functional + Iddq Ship (truly good) Reject bin (caught) ESCAPE → DPPM CourseTron · coursetron.com
    A defective die that the test program fails to sensitize slips down the dashed path and becomes a field DPPM contributor.

    How DPPM is calculated

    DPPM is simply the number of defective units confirmed per million shipped:

    DPPM = (defective units returned / total units shipped) × 1,000,000. If 7 of 3.5 million shipped parts are confirmed defective on customer analysis, that is exactly 2 DPPM.

    Two subtleties trip up engineers. First, DPPM is reported against confirmed defects after failure analysis — "no trouble found" returns are excluded, which is why FA throughput gates how fast you can learn. Second, the denominator and the clock matter: a 90-day field DPPM and a lifetime DPPM for the same lot are different numbers because latent defects emerge over the bathtub curve.

    Worked DPPM example 7 confirmed defective ÷ 3,500,000 shipped × 1,000,000 = 2 DPPM Only failure-analysis-confirmed defects count CourseTron · coursetron.com
    Worked example from the text: 7 confirmed defective parts out of 3.5 million shipped is exactly 2 DPPM.

    The levers that actually move the number

    TechniqueWhat it catchesTypical tooling
    Stuck-at ATPGHard opens/shorts, logic-level faultsSynopsys TestMAX, Siemens Tessent
    Transition / SDD patternsResistive opens, slow-to-switch netsTessent, Cadence Modus
    Iddq / IddtBridging, gate-oxide leakageQuiescent current measurement on ATE
    Cell-aware / defect-based testIntra-cell shorts GDSII-extractedTessent CellModelGen
    Burn-in / system-level testLatent, time-dependent failuresSLT rigs, HTOL

    The progression is deliberate: you add fault models that target the mechanisms escaping you, confirmed by failure analysis on actual returns. Cell-aware test, for example, extracts likely short and open locations from the standard-cell layout and generates patterns specifically for them — turning a vague "logic coverage" into coverage of real silicon failure modes. This is where a tight loop with Avecas design-for-test services pays off, because DFT structure decided at RTL dictates how low DPPM can ever go downstream.

    Screening the walking wounded: outlier methods

    Many escapes are not coverage failures at all — the part passed every spec limit but was abnormal relative to its neighbors. Statistical outlier detection catches these marginal dies even though no single test exceeded its guardband:

    • PAT (Part Average Testing): set dynamic limits at the lot mean ±6σ on a parameter such as leakage. A die inside the hard spec but 8σ off the lot mean is binned out.
    • GPAT / DPAT: geographic and dynamic variants that account for wafer-position systematics so you do not over-reject good edge die.
    • NNR (Nearest-Neighbour Residual): compare a die to its physical neighbours; a lone leaky die in a quiet region is suspect.
    • Composite / multivariate outlier screens that combine many parametric tests to find the die that is subtly odd on several axes at once.
    Outlier die: inside hard spec, outside PAT Iddq leakage → lot population PAT ±6σ hard spec a die passes hard spec… …but trips PAT CourseTron · coursetron.com
    Animated: a marginal die drifts well inside the hard spec limit yet beyond the dynamic PAT limit — exactly the "walking wounded" an outlier screen removes before it becomes a field escape.

    Outlier screening is a yield-versus-quality trade. Tighten limits and DPPM falls but you scrap good dies; loosen them and yield rises at the cost of escapes. The right operating point is set by the customer's quality contract and the cost of a field return, and it is continuously re-tuned as new defect modes surface. This is the same data that feeds yield analysis and failure-analysis workflows — the three disciplines share one database.

    Closing the loop

    Lowering DPPM is an iterative post-silicon program, not a one-time test-list fix. Every confirmed field return is failure-analyzed, the defect mechanism identified, mapped back to a coverage or screening gap, and a new pattern set or outlier rule added. Over a product's life this ratchets DPPM down from the hundreds at ramp to single digits in mature production.

    Want to design test programs that actually hit automotive DPPM targets? The CourseTron Post-Silicon Validation track walks through ATPG coverage, outlier screening, and FA-driven loop closure with real ATE data. Explore the courses →

    Frequently asked questions

    Is DPPM the same as yield loss?

    No. Yield loss counts parts you reject at test; DPPM counts defective parts you shipped that the test missed. You can have high yield and bad DPPM simultaneously — that usually means your test coverage is too low, not that your silicon is clean.

    Why not just add more patterns until coverage is 100%?

    Test time is money on the ATE, and stuck-at coverage saturates well before it catches timing or leakage defects. Beyond a point you get more quality per second by switching fault models (transition, cell-aware, Iddq) and adding outlier screens than by piling on stuck-at vectors.

    What DPPM target is "good"?

    It depends on the end market. Consumer parts may accept hundreds of DPPM; industrial sits in the tens; automotive AEC-Q100 and safety-critical datacenter parts push for under 1 DPPM, which forces system-level test and aggressive outlier screening.

    Do outlier methods reject good parts?

    Some, yes — that is the deliberate cost. A well-tuned PAT/NNR flow scraps a small fraction of genuinely good dies to remove the marginal ones most likely to fail in the field, and the limits are set from the economics of a field return versus a scrapped die.

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