In short: Failure analysis isolates a silicon defect by narrowing from an electrical symptom to a physical location (fault isolation), exposes the die (decapsulation), and then images or cross-sections the suspect site (SEM/FIB) to establish an unambiguous root cause that feeds back into design and process fixes.
When a chip fails in the lab, in qualification, or back from a customer, the question is never just "is it broken?" — it is "where, why, and is it systematic?" A single failing part can represent a mask defect that will sink an entire wafer lot, or a one-off ESD event. Failure analysis (FA) is the disciplined funnel that turns an ambiguous electrical complaint into a photograph of the actual defect and a verifiable root cause. This article walks the standard FA flow used across post-silicon teams, with the real tools and numbers you will be asked about in interviews.
The FA funnel: from symptom to atom
FA is destructive and expensive, so it proceeds non-destructive first. The golden rule: never remove material until you have localized the suspect region, because every etch step destroys evidence you cannot recover. The sequence is almost always verification → fault isolation → sample prep (decap) → physical imaging → root cause.
Fault isolation: finding the hot spot electrically
Before any grinding, FA engineers use electrical and optical techniques to pin the fault to a region often smaller than 1 µm. The workhorses:
- Photon emission microscopy (EMMI / PEM): a biased defect leaks current and emits faint near-IR photons (leaky junctions, latch-up, gate-oxide pinholes). A cooled InGaAs camera integrates for seconds to minutes and overlays the emission on the layout.
- OBIRCH / thermal laser stimulation: a scanning 1,340 nm laser locally heats metal; a resistive defect (void, via crack) changes the supply current, mapping the anomaly.
- Design-based diagnosis: for logic, scan-chain and ATPG diagnosis (Siemens Tessent Diagnosis, Synopsys TetraMAX/Yield Explorer) back-trace failing patterns to candidate nets — the bridge between test and physical FA.
Key fact: Modern scan diagnosis can resolve a logic failure to a handful of candidate nets with sub-micron accuracy from the ATE fail log alone — no physical prep required to decide where to cut.
Localization only tells you where. To learn why, you must see the silicon. On flip-chip packages, fault isolation is done through the thinned backside (silicon is transparent at IR), so backside sample prep (lapping to ~30–100 µm) often precedes emission work.
Decapsulation: exposing the die without destroying it
For wire-bonded plastic (epoxy) packages, decap chemically removes the mold compound to expose the die and bond wires intact. The classic method is a jet of hot (>90 °C) fuming nitric or sulfuric acid in an automated decapsulator, timed to stop at the passivation. Laser pre-ablation thins the cavity first to cut acid exposure. The failure modes you are protecting against:
- Over-etch that lifts bond wires or dissolves aluminum pads — destroying the very open you were chasing.
- Acid attack on copper pillars in advanced packages, which is why many labs prefer plasma (O₂/CF₄) decap for Cu.
SEM and FIB: imaging the defect
With the site exposed and delayered (wet etch or plasma, layer by layer), physical imaging takes over. A scanning electron microscope (SEM) resolves features down to a few nanometers, far past the diffraction limit of optical microscopes (~200 nm). But many defects live inside a stack — a void in a tungsten via, a thin-gate oxide rupture — and are invisible from the top.
That is where the focused ion beam (FIB) earns its place. A gallium (or newer plasma Xe) ion column mills a trench exactly at the coordinate flagged by fault isolation, producing a clean cross-section that the SEM then images. Dual-beam FIB-SEM systems (Thermo Fisher Helios, Zeiss Crossbeam) do both in one chamber. FIB also enables circuit edit: cutting a metal line or depositing a tungsten jumper to prove a hypothesized fix on actual silicon before a mask respin that costs weeks and lakhs of rupees.
Comparing the core techniques
| Technique | Resolution | Destructive? | Best for |
|---|---|---|---|
| EMMI (photon emission) | ~0.5–1 µm | No | Leakage, junction, oxide defects |
| OBIRCH (laser) | ~1 µm | No | Resistive opens, via/metal cracks |
| Optical microscope | ~200 nm | No | Gross defects, delayer inspection |
| SEM | ~1–5 nm | Mild | Surface / delayered morphology |
| FIB-SEM | ~5 nm (cross-section) | Yes | Buried voids, circuit edit |
| TEM | <0.1 nm | Yes | Gate oxide, thin-film, atomic lattice |
Key fact: When a 1–2 nm gate-oxide layer is the suspect, even a FIB cross-section is too coarse — the sample is FIB-thinned to an electron-transparent lamella (<100 nm) and imaged in a TEM, the only tool with true atomic resolution.
Root cause and the feedback loop
The deliverable of FA is not a picture — it is a classified root cause tied to an action. Teams bin findings into design-related (EM/IR weakness, antenna, marginal timing exposed by voltage/temperature), process-related (mask defect, CMP dishing, via void, contamination), and use-related (ESD/EOS, latch-up, mechanical stress). An FA report that says "metal-3 via void over cell U1234, process signature, 7 of 7 failing units" lets the fab correlate to a specific tool and chamber. A single-unit ESD finger-print, by contrast, closes as non-systematic. This root-cause classification is what separates a yield-saving FA lab from an expensive microscope.
FA ties directly into earlier post-silicon work — see our note on device characterization for how shmoo plots and corner testing surface the marginal conditions that FA then localizes, and post-silicon validation and bring-up for how first-silicon debug feeds the FA queue. For the full toolchain, browse our post-silicon course catalog. Teams that also need silicon design support often partner with Avecas VLSI design services to close the loop between a confirmed defect and an ECO or respin.
Go deeper: CourseTron's Post-Silicon Validation & Failure Analysis track takes you hands-on through EMMI reading, decap safety, and FIB cross-section planning with real fail logs. Explore the course →
Frequently asked questions
Why localize before decapsulating?
Because decap and delayering are irreversible. If you remove material before knowing where the defect is, you can etch straight through the evidence. Fault isolation (EMMI, OBIRCH, scan diagnosis) narrows the suspect area to roughly 1 µm so the physical prep is surgical, not exploratory.
What is the difference between SEM and FIB?
An SEM images with electrons and only sees the surface it is pointed at. A FIB mills with ions, so it can cut a precise trench to expose buried structure — then a dual-beam system uses its SEM column to image that fresh cross-section. FIB also edits circuits; SEM only observes.
When do you need a TEM instead of a FIB-SEM?
When the feature is a few nanometers thick — gate oxides, high-k dielectrics, thin barrier metals. FIB-SEM resolves ~5 nm; a TEM resolves below 0.1 nm but requires an electron-transparent lamella, which is itself prepared by FIB thinning.
Is failure analysis used for a single failing part or for yield?
Both, and the distinction is the point. FA classifies a defect as systematic (process signature repeating across units and wafers) or random (one-off ESD/EOS). Systematic findings drive fab corrective action and save yield; random ones close as isolated events.