In short: Known-good-die (KGD) is the practice of fully testing a bare, unpackaged die to a quality level equivalent to a packaged part, so that only proven-good dice are committed into expensive multi-die assemblies like 2.5D interposers, 3D stacks and HBM cubes.
Why a Single Bad Die Can Sink a $10,000 Package
In a classic single-chip product, you test the die, and if it fails you throw away one die. The economics are forgiving. In advanced packaging the calculus inverts completely. When you stack eight DRAM dice on a base logic die to build an HBM3 cube, or place a 600 mm² GPU next to four HBM stacks on a silicon interposer, the assembly represents thousands of dollars of good silicon, substrate and bonding labor. If any one die in that assembly is defective and you only discover it after bonding, you scrap the entire module. This is the compound-yield problem that makes KGD not a nicety but a survival requirement.
The math is unforgiving. If each die enters assembly with a yield (probability of being good) of y, and you combine n dice, the assembly yield is roughly yn (assembly defects aside). For an 8-high HBM stack plus a base die (n=9), even 99% per-die quality gives 0.999 ≈ 91.4% — nearly one in eleven cubes lost. At 95% per-die, you keep only 63%. Push per-die quality to 99.9% and you recover 99.1%. That is the entire business case for KGD in one line.
For a 12-high HBM stack, improving incoming die quality from 99.0% to 99.9% raises stack yield from about 88.6% to 98.8% — a ~10-point swing that, on a product selling for hundreds of dollars per cube, dwarfs the cost of the extra wafer-level test.
What "Known Good" Actually Means
A packaged part earns its quality rating through a full regime: structural tests (scan, MBIST), functional/at-speed tests, parametric (IDDQ, leakage, I/O timing), and — crucially for reliability — burn-in, which accelerates infant-mortality failures by stressing the part at elevated voltage and temperature. The hard part of KGD is reproducing that regime on a bare die, before packaging, where you have no package pins to probe and no socket to grip.
Historically, KGD was dominated by temporary carriers and specialized membrane probe cards that let a bare die be burned in and tested as if it were packaged. Modern flows push as much of this as possible to wafer-level test (WLT) and wafer-level burn-in (WLBI), where the whole wafer is contacted at once on advanced probe cards (e.g., MEMS or vertical-spring cards from FormFactor or Technoprobe) and exercised with built-in self-test.
DFT Is the Enabler: Making a Bare Die Testable
You cannot brute-force test a die with a few thousand micro-bumps using external pattern application alone — there simply are not enough accessible probe points, and the bumps are too fragile and dense. Design-for-test (DFT) is what makes KGD practical:
- Scan + compression (Synopsys DFTMAX/TestMAX, Siemens Tessent) squeezes millions of scan cells behind a handful of channels so stuck-at and transition faults are covered with minimal pins.
- Memory BIST (MBIST) self-tests the DRAM/SRAM arrays on-die — essential for HBM, where the die is almost entirely memory.
- IEEE 1838 defines a 3D test access architecture, including the die wrapper and a serial/parallel port so each die in a future stack can be isolated and tested, and so inter-die bonds can be checked after stacking.
- IEEE 1687 (IJTAG) standardizes access to embedded instruments (sensors, BIST engines) through the test network.
For HBM, the base logic die carries test and repair logic that runs MBIST across all stacked DRAM dice and applies spare-row/column redundancy. Post-bond repair at the stack level is a second yield-recovery lever layered on top of incoming KGD quality.
The Cost and Coverage Trade-off
KGD is not free. Wafer-level burn-in, thermal probe cards and extra test insertions add cost and throughput pressure. The engineering question is always: how much test do I apply to the bare die versus relying on post-stack test and repair? The answer depends on n, on part value, and on how much redundancy the design carries.
| Assembly | Dice (n) | Per-die quality | Approx. assembly yield |
|---|---|---|---|
| Single SoC | 1 | 95% | 95% |
| 2.5D: GPU + 4 HBM | 5 | 98% | ~90.4% |
| 8-high HBM + base | 9 | 99% | ~91.4% |
| 8-high HBM + base | 9 | 99.9% | ~99.1% |
| 12-high HBM + base | 13 | 99.9% | ~98.7% |
This is why the industry invests so heavily in squeezing defect levels into the tens-of-DPPM (defects per part per million) range for dice destined for stacking, where a single-chip consumer part might tolerate several hundred DPPM. The target quality is set by the assembly, not the die.
KGD in the 2.5D / 3D Flow
In a practical heterogeneous-integration flow, KGD lives at several points. First, pre-bond test at the wafer level screens each die type (logic, memory, I/O chiplet) to its KGD target. Then dice are thinned, TSVs are revealed, and dice are bonded. Mid-bond and post-bond test using the IEEE 1838 die wrapper verify that the inter-die microbumps and TSVs connect correctly and that no die was damaged by thinning or bonding stress. Finally, post-stack repair maps out failed memory rows. KGD is the gate that keeps the garbage out before all that value is committed.
Teams building these flows lean on ATE platforms (Advantest V93000, Teradyne UltraFLEX) driving patterns generated by VLSI test-engineering training programs like ChipXpert, with DFT inserted earlier in the design by Tessent or TestMAX. If you want the design-side counterpart — inserting the scan, BIST and 1838 structures correctly — Avecas design services handle that DFT architecture work.
Where KGD Connects to the Rest of Post-Silicon
KGD does not stand alone. Its targets are derived from yield analysis, which tells you how good your dice actually are and where defects cluster on the wafer. And the patterns that do the screening come from the same ATPG and fault-model work covered in our scan-chain diagnosis material. Together these form the post-silicon quality chain. For the full structured path through test, DFT and packaging, see our course catalog.
FAQ
Is KGD the same as wafer sort?
No. Wafer sort (probe test) is one component, but KGD demands packaged-equivalent quality including burn-in and reliability screening, applied to the bare die. Plain wafer sort typically does not reach the DPPM levels that stacking requires.
Why is KGD so critical for HBM specifically?
Because an HBM cube stacks 8–12 DRAM dice plus a base die. Compound yield means that even small per-die defect rates multiply into large cube losses, and once bonded, a single bad die scraps the whole cube. High incoming die quality plus post-stack redundancy repair is the only economic path.
How do you burn in a bare die with no package?
Either with temporary carriers/sockets that hold the die during burn-in, or increasingly with wafer-level burn-in, where an advanced probe card contacts all dice on the wafer at elevated voltage and temperature so infant-mortality defects are screened before dicing.
What DFT standard governs testing dice inside a 3D stack?
IEEE 1838 defines the 3D test access architecture, including a per-die wrapper and serial/parallel test ports, so each die can be isolated for pre-bond test and the bonds verified post-bond. It is typically used alongside IEEE 1687 (IJTAG) for instrument access.
Ready to master wafer-level test, DFT insertion and advanced-packaging quality end to end? Explore CourseTron's Post-Silicon Validation & Test track — it walks through KGD, scan/BIST and HBM stacking with real ATE and tool examples. Browse the courses →