In short: Scan diagnosis replays the failing scan patterns against a fault-simulated netlist to rank the gates or scan-chain segments most likely holding the defect, letting you steer a FIB or e-beam cut to a handful of suspect nets instead of the whole die.
When a chip fails on the ATE, the tester hands you a datalog, not a defect location. The job of scan diagnosis is to convert those failing cycles into a short, ranked list of physical suspects you can hand to a failure-analysis (FA) lab. Because modern SoCs embed thousands of scan flops stitched into dozens of chains and wrapped in logic-BIST or compression hardware, doing this by hand is impossible. Tools such as Siemens EDA Tessent Diagnosis, Synopsys TetraMAX/Z01X, and Cadence Modus run the algorithms that make it tractable.
Two problems hiding in one datalog
The first decision in any diagnosis flow is whether the defect lives in the scan chain itself (the shift path of flops and their clock/reset network) or in the combinational logic between chains (the functional cloud captured during the capture cycle). These demand different diagnosis engines, and mixing them up wastes FA budget.
The giveaway is simple. Run a dedicated chain test first: shift a known pattern — classically 00110011… — straight through each chain with no capture. If a chain cannot pass this flush, the defect is in the shift path, and logic diagnosis results from that chain are untrustworthy because every observe point downstream of the break is corrupted.
Chain diagnosis: reading the shift path
Chain diagnosis exploits a neat property. A chain is just a shift register, so if cell N is stuck, every value loaded behind it (closer to scan-in) still passes through the good cells ahead of it, while values that must pass through N are corrupted. By applying both an all-0 and an all-1 flush and watching where the expected/observed streams diverge, the tool brackets the fault to a specific cell or the net between two cells. Tessent and Modus report this as an upper and lower cell bound plus a fault type: stuck-at-0, stuck-at-1, slow-to-rise (a timing/transition defect that only misses at speed), or an intermittent fast-to-fall.
Rule of thumb: roughly 10–30% of scan-related failures are chain defects, not logic defects. Always diagnose the chain integrity first — logic diagnosis on a broken chain produces confident nonsense.
Logic diagnosis: the effect-cause method
For failures that capture correctly through good chains, tools use an effect-cause approach. The flow is roughly:
- Read the failing bits. Each failing (pattern, scan-cell) pair is an observed symptom at a known observe point.
- Backtrace. From each failing flop, trace the logic cone back through the fanin to the set of nets whose corruption could explain that capture value.
- Intersect the cones. A real single defect must sit in the intersection of the cones of all patterns it fails — and must not explain patterns that passed.
- Fault-simulate candidates. The tool injects candidate faults and simulates the full test set, scoring each by how well its simulated fail set matches the measured one.
Two metrics drive the ranking. Diagnostic resolution is how many suspects you end up with (fewer is better; a resolution of 1–3 nets is excellent). Diagnostic accuracy is whether the true defect is actually in that list. A report with 50 equally-scored suspects has poor resolution and is nearly useless to the FA lab.
Defect models beyond stuck-at
Early diagnosis assumed single stuck-at faults. Real silicon rarely cooperates. Modern tools fit the failure to richer models:
| Behavior | Model | Typical physical cause |
|---|---|---|
| Fails only at speed | Transition / slow-to-rise-fall | Resistive via, weak contact |
| Fails as a function of neighbors | Bridge (AND/OR/dominant) | Shorts between adjacent metal |
| Pattern-dependent, non-monotonic | Open / net-level | Floating node, broken via chain |
| Correlates with a cell type | Cell-internal / layout-aware | Defect inside a standard cell |
Layout-aware diagnosis is the current state of the art: the tool ingests the physical LEF/DEF and the extracted parasitics, so a bridge suspect is only reported if two nets are actually adjacent on silicon. This routinely cuts suspect counts in half and is what makes volume diagnosis useful for yield learning.
Volume payoff: run diagnosis across hundreds of failing dies and a histogram of suspect locations will spot a systematic defect — a weak via rule or a litho hotspot — long before classic PFA could, feeding fixes back to the fab.
A concrete walk-through
Suppose a 7 nm networking die fails 6 of 40,000 at-speed transition patterns, all on chain 12, and the chain flush passes clean. Logic diagnosis backtraces the six failing flops, intersects their cones, and fault-simulates. It returns two suspects scored 0.94 and 0.31, both transition faults on nets physically adjacent in metal-3. The 0.94 suspect explains all six fails and no passing patterns; the 0.31 explains only four. You hand the FA lab one net. Under a focused-ion-beam and passive-voltage-contrast inspection they find a partially-formed via — exactly the resistive-open signature a slow-to-rise model predicts. That is the whole value proposition: six tester fails became one coordinate on the die.
Where it connects to the rest of post-silicon
Scan diagnosis is one instrument in a larger kit; it hands off to physical FA and feeds yield analytics. For the broader bring-up and bench methods it sits next to, see our companion piece on silicon debug techniques, and for the pattern side that produces the tests you replay, read ATPG fundamentals. Engineers building this skill for interviews often pair it with hands-on flows from a structured program such as our VLSI training partner ChipXpert's post-silicon track.
Want to run real Tessent and TetraMAX diagnosis flows on seeded-defect designs? The CourseTron Post-Silicon & DFT course walks you through chain diagnosis, layout-aware logic diagnosis, and volume yield learning on industry tools.
Frequently asked questions
Why diagnose the scan chain before the logic?
A broken shift path corrupts every observe point behind the break, so logic diagnosis will confidently point at the wrong nets. A clean chain flush test is the precondition for trusting any logic-diagnosis report.
What limits diagnostic resolution?
Low fault coverage, pattern masking from compression, aliasing in the MISR, and multiple simultaneous defects all inflate the suspect count. More distinct failing patterns per defect generally sharpen resolution.
Is diagnosis the same as PFA?
No. Diagnosis is a software step that produces ranked electrical suspects. Physical failure analysis (FIB, SEM, PVC) is the lab work that confirms the defect at a suspect location. Diagnosis makes PFA affordable by shrinking the search area.
Can I diagnose through test compression?
Yes. Tools reverse the compaction (EDT/XTOL-style) to map compressed fail signatures back to internal scan cells, though heavy compaction and masked bits reduce achievable resolution.