Four Layer PCB Stackup

In short: A 4-layer signal–ground–power–signal stackup gives every fast signal a continuous reference plane one dielectric away, which is why it is the minimum trustworthy foundation for reliable digital boards running above a few tens of megahertz.

Ask any seasoned hardware engineer why their 100 MHz microcontroller board "just worked" while a colleague's 2-layer attempt radiated like an antenna and failed EMC, and the answer almost always comes back to the stackup. The jump from two copper layers to four is the single highest-leverage decision in digital PCB design, and the classic arrangement — signal, ground, power, signal — is the reason. This article explains that stackup layer by layer, with the physics and the numbers that matter when you sit down in Cadence Allegro, Siemens Xpedition, or Altium to define it.

Why two layers runs out of road

On a 2-layer board, your return current has no dedicated plane. A trace on the top layer references whatever copper happens to be below it — often a sparse ground pour broken by other traces and vias. The return current, which always wants to flow directly beneath the signal (the path of least impedance at high frequency), is forced to detour around gaps. Each detour grows the loop area, and loop area is directly proportional to both radiated emissions and susceptibility to coupled noise.

Consider a 50 MHz clock with 1 ns edges. Its significant harmonic content reaches roughly 0.35/t_r ≈ 350 MHz. At those frequencies even a few millimetres of return-path discontinuity turns into measurable inductance and a failed radiated-emissions scan at 3 metres. Four layers fix this structurally rather than by luck.

The S-G-P-S arrangement, layer by layer

Reading top to bottom, the four copper layers are assigned as follows:

• L1 — Signal. Carries your fastest, most critical nets (clocks, strobes, DDR, high-speed serial) because it sits directly above the ground plane.
• L2 — Ground. A solid, unbroken copper pour. This is the reference plane for L1 and the single most important layer on the board.
• L3 — Power. A solid plane (or split planes for multiple rails). Together with L2 it forms a parallel-plate capacitor.
• L4 — Signal. The second routing layer, referenced to the power plane; use it for slower nets and escape routing.

Key fact: Keep the L1 ↔ L2 and L3 ↔ L4 prepreg thin (often 0.1–0.2 mm) and the L2 ↔ L3 core thick (around 1.0 mm). This "asymmetric" build gives tight signal-to-reference coupling on the outer layers while keeping the overall board at a standard 1.57 mm finished thickness.

What the ground plane actually buys you

With a solid plane one dielectric below every outer-layer trace, the high-frequency return current flows in a tight image directly under the signal. The loop area collapses to essentially the dielectric thickness times the trace length — tens of times smaller than a 2-layer equivalent. Smaller loops mean lower partial inductance, lower crosstalk, and dramatically lower radiated emissions. The same geometry also defines a predictable, controllable characteristic impedance, which you cannot achieve without a reference plane.

A microstrip trace on L1 over L2 at a dielectric height of 0.1 mm (FR-4, ε_r ≈ 4.3) needs a width of roughly 0.18 mm to hit 50 Ω single-ended. Field solvers built into Siemens HyperLynx, Cadence Sigrity, or Polar Si9000 compute this exactly; the point is that a plane makes the number solvable and repeatable from board to board and fab to fab.

The power–ground plane pair as a capacitor

Because L2 and L3 are large overlapping copper sheets separated by a thin-ish core, they form a built-in decoupling capacitor. The capacitance is C = ε₀ε_r A/d. For a 100 cm² overlap at d = 0.5 mm this is only around 760 pF — small, but it has near-zero inductance and so supplies charge at frequencies where discrete capacitors have already gone inductive. It complements, never replaces, your bank of discrete decoupling caps.

Key fact: A modest 30–60% bare-board cost premium for the extra two layers routinely saves weeks of EMC re-spins. On any board that must pass FCC/CE radiated-emissions testing, four layers is the cheaper option once engineering time is counted.

Design rules that keep the stackup honest

• Never split the ground plane under a fast net. A slot forces the return current to loop around it, creating a gap-crossing discontinuity that behaves like a tuned slot antenna.
• Watch layer-change return paths. When a signal vias from L1 to L4, its return reference changes from ground to power. Place stitching capacitors or ground vias nearby so the return current has a low-impedance way across.
• Route orthogonally where both layers carry signals to minimise broadside crosstalk, and keep high-speed nets on L1 (over ground) by preference.
• Specify the stackup to your fab. Copper weight, prepreg, and core affect ε_r and impedance — confirm the actual build before trusting your field-solver numbers.

If you want the deeper layer-assignment theory and when to step up to six or eight layers, our companion guide on PCB stackup layers walks through the general framework, and the piece on controlled impedance routing covers the trace-geometry math in detail. Teams that also need their boards manufactured and signal-integrity-verified often lean on specialist PCB and VLSI design services from Avecas for production-grade sign-off.

Want to design boards that pass EMC on the first spin? Our CourseTron PCB & Signal Integrity course walks you through stackup planning, impedance control, and return-path analysis with real field-solver labs.

Frequently asked questions

Why is ground on L2 and not power?

Your fastest signals live on L1, and they need the quietest, most continuous reference directly beneath them. Ground is that reference. Putting ground on L2 keeps the critical high-speed return path adjacent to the nets that matter most.

Can I swap to signal-power-ground-signal instead?

It works, but then your top-layer fast nets reference the power plane, which is noisier and often split into multiple rails — a split directly under a clock is a classic EMC failure. S-G-P-S keeps the best reference next to the most critical layer, so it is the safer default.

Does a 4-layer board remove the need for decoupling capacitors?

No. The plane-pair capacitance (often under 1 nF) only helps at very high frequencies. You still need bulk and local decoupling capacitors across the spectrum; the planes complement them.

When should I go beyond four layers?

When you run out of routing room for fast nets that all need a ground reference, have many power rails, or carry high-speed differential pairs that need dedicated stripline layers — typically DDR3/DDR4, multi-gigabit SerDes, or dense BGAs.