In short: Characteristic impedance is set by the geometry around a trace — its width and copper thickness, the height to the nearest reference plane, and the dielectric constant of the material between them — so hitting 50 Ω single-ended or 100 Ω differential is a controlled-stackup problem, not an afterthought.
Every high-speed net on a modern PCB is a transmission line, and the moment edge rates fall below roughly 1 ns the board stops behaving like a lumped wire. The signal now cares about the impedance of the path it travels, and any abrupt change in that impedance reflects energy back toward the source. Controlling impedance means controlling the cross-sectional geometry so the trace presents a constant, predictable value — almost always 50 Ω for single-ended nets and 90–100 Ω for differential pairs like USB, Ethernet, PCIe and DDR.
What actually sets the impedance
Characteristic impedance (Z₀) is governed by the distributed inductance and capacitance per unit length: Z₀ = √(L/C). You never compute L and C by hand on a real board — you drive the four geometric knobs that move them:
- Trace width (w) — wider copper raises capacitance to the plane and lowers impedance.
- Dielectric height (h) — the distance from the trace to the nearest reference plane. More height raises impedance.
- Dielectric constant (Dk / εr) — the permittivity of the laminate. Higher Dk lowers impedance.
- Copper thickness (t) — thicker copper slightly lowers impedance and adds edge-coupling.
Key fact: Width and height dominate. A good mental model for a microstrip is that Z₀ tracks h/w — push the plane away or thin the trace and impedance climbs; widen the trace or pull the plane closer and it drops.
A worked 50 Ω microstrip
Take a common outer-layer stack: a 1-oz trace (t ≈ 35 µm) over an FR-4 prepreg with Dk ≈ 4.2 at 1 GHz, and a plane 100 µm (about 3.9 mil) below. A field solver gives roughly 50 Ω at a trace width near 180 µm (7 mil). Now imagine the fab substitutes a thinner prepreg so h drops to 75 µm. Impedance falls to about 43 Ω — a 14 % miss that will show up as reflections on a gigabit link. To recover 50 Ω you must also narrow the trace to roughly 5.5 mil. This coupling is exactly why you quote a stackup, not just a trace width, to the fabricator.
| Change | Effect on Z₀ | Why |
|---|---|---|
| Wider trace (↑w) | ↓ lower | more capacitance to plane |
| Thicker dielectric (↑h) | ↑ higher | field weakens, less C |
| Higher Dk (↑εr) | ↓ lower | permittivity raises C |
| Thicker copper (↑t) | ↓ slightly | added edge capacitance |
Microstrip vs. stripline
An outer-layer microstrip sees air above and dielectric below, so it carries an inhomogeneous "effective Dk" somewhere between the two. It is faster (lower effective permittivity) but radiates more and is exposed to solder-mask variation — mask over copper typically drops Z₀ a couple of ohms. A stripline buried between two planes is fully embedded in dielectric: more stable, better shielded, but slower and harder to rework. Memory and backplane designers lean on stripline for the critical nets precisely because the geometry is tightly bounded on all sides.
Key fact: FR-4 Dk is frequency-dependent — around 4.4 at 100 MHz but closer to 4.0–4.2 at multi-GHz. For 56G SerDes you move to low-loss laminates (Megtron 6, Tachyon, Isola I-Tera) with Dk near 3.0–3.5 and a far lower dissipation factor (Df) to keep loss manageable.
Differential pairs: the spacing knob
A differential pair adds one geometric variable: the edge-to-edge spacing (s) between the two traces. Differential impedance (Zdiff) is roughly twice the odd-mode impedance, and tightening the spacing increases the coupling between the two conductors, which lowers Zdiff. So for a 100 Ω pair you co-optimise w, h and s together — widen the traces to drop each line toward ~50 Ω single-ended, then set the gap for the coupling you want. Loose coupling (s > 2w) makes each trace behave almost independently and is more tolerant of etch variation; tight coupling saves routing area but is unforgiving. The art of placing, length-matching and gap-controlling those pairs is covered in our deep dive on differential pair routing.
Designing the stackup for control
Controlled impedance begins at the stackup table, before any routing. You and the fabricator agree on layer count, copper weights, prepreg/core thicknesses and the laminate's Dk/Df, then a 2D field solver — the one inside Polar Si9000, Siemens HyperLynx, Cadence Allegro, or Synopsys/Ansys tools — computes the trace widths that land on target. The fab returns an impedance-controlled stackup drawing, and a test coupon on the panel is measured with a TDR (time-domain reflectometer) to confirm the real boards fall inside the ±10 % (often ±7 %) tolerance window. Teams building production-grade boards, like the design group at Avecas design services, treat this coupon measurement as a gate, not a nicety.
A few practical rules keep the geometry honest: always route high-speed traces directly over a continuous plane (never across a split), keep the reference plane on an adjacent layer so h is small and well-defined, and account for solder-mask and surface-roughness effects that a bare-copper solver ignores. When you must change layers, place return-path stitching vias so the loop inductance — and therefore Z₀ — stays continuous. More layout discipline for these transitions lives in our guide to high-speed via stitching.
Want to go from formulas to a fabricated, TDR-verified board? The CourseTron High-Speed PCB & Signal Integrity track walks you through stackup design, field solving and impedance measurement on real hardware.
Frequently asked questions
Why 50 Ω and not some other value?
50 Ω is a historical compromise for coax between lowest loss (~77 Ω) and highest power handling (~30 Ω), and it became the connector/instrument standard. Boards match it so traces, connectors and test gear all share one reference.
Does trace length change characteristic impedance?
No. Z₀ is a per-unit-length property of the cross-section, so a longer trace has the same impedance — length only adds delay and loss. What matters is keeping the geometry constant along the whole run.
How much does FR-4 Dk tolerance hurt me?
FR-4 Dk can vary ±0.2 or more between lots and with frequency, which alone can swing Z₀ by several percent. That is why you budget tolerance, quote a stackup, and verify with a TDR coupon rather than trusting a single calculated number.
Microstrip or stripline for my fastest nets?
Use stripline when you need the tightest impedance control and shielding (backplanes, DDR fly-by); use microstrip when speed and easy rework matter and some radiation is acceptable. Many boards mix both across layers.