In short: A PCB stackup's layer count and — more importantly — the ordering of its signal and plane layers set every trace's reference impedance, the loop inductance of its power delivery, and how strongly adjacent signals couple, so a well-ordered 4- or 6-layer board routinely outperforms a carelessly arranged one with more copper.
Ask any hardware engineer why their first 2-layer prototype worked on the bench but radiated like an antenna in the EMC chamber, and the answer is almost always buried in the stackup. The number of copper layers is the visible decision; the order of those layers is the one that quietly governs signal integrity, power integrity, and electromagnetic compatibility. This article walks through the canonical 2-, 4-, and 6-layer stackups, with the concrete numbers and reasoning you need for a design review — or an interview.
What a stackup actually controls
A stackup is the vertical arrangement of copper layers and the dielectric (usually FR-4, with a relative permittivity εr near 4.3 at 1 GHz) between them. Three physical quantities fall straight out of it:
- Characteristic impedance (Z0) — set by trace width, copper thickness, and the distance to the nearest reference plane. A 50 Ω single-ended microstrip over FR-4 needs roughly a 2:1 width-to-height ratio; move the plane farther away and the trace gets wider.
- Power-delivery loop inductance — the tighter the power and ground planes are stacked, the lower the plane-pair inductance and the better the decoupling at high frequency.
- Crosstalk — coupling between neighbouring traces that share, or fail to share, a clean return path.
Rule of thumb: every signal layer should have a solid, uninterrupted reference plane directly adjacent to it. The return current flows in that plane, image-like, right under the trace. Break the plane and you break the return.
The 2-layer board: cheap, but no real reference
A 2-layer board is two copper sheets on a ~1.5 mm core. Impedance control is poor: a signal on top referenced to a ground pour on the bottom sits 1.5 mm away, which forces trace widths around 2.8 mm for 50 Ω — impractical. In practice 2-layer boards are used below a few tens of MHz, for power supplies, simple MCU boards, and hobby work. The return current is forced to meander around pours and splits, so loop area — and therefore radiated emissions — balloons. Decoupling relies entirely on discrete capacitors because there is no low-inductance plane pair.
The 4-layer board: the workhorse
The jump to four layers is the single biggest signal-integrity upgrade you can buy. The standard order is SIG — GND — PWR — SIG. Each outer signal layer references an adjacent plane only ~0.1–0.2 mm away, so 50 Ω traces shrink to roughly 0.25 mm and impedance becomes genuinely controllable. The GND and PWR planes form a buried capacitor that supplies fast transient current.
Plane ordering matters even here. Putting GND directly under the top signal layer (where your fast ICs and clocks usually live) gives those critical nets a clean, continuous return. A common mistake is SIG — PWR — GND — SIG, which references your most sensitive top-layer signals to a cut-up power plane — every power split becomes a return-path discontinuity and a crosstalk/EMI source.
The 6-layer board: room to do it right
Six layers let you give high-speed signals a plane on both sides (stripline) and still keep a tight power/ground pair. A strong order is SIG — GND — SIG — SIG — PWR — SIG, or the quieter SIG — GND — SIG — PWR — GND — SIG when you can afford two ground planes. The second form gives you two reference planes framing the inner signal layers and the lowest plane-pair inductance, at the cost of one routing layer.
How ordering drives impedance, decoupling and crosstalk
| Effect | Driven by | Design lever |
|---|---|---|
| Impedance Z0 | Trace-to-plane spacing & εr | Thin prepreg to the adjacent plane; solve with a field solver |
| Decoupling | PWR/GND plane separation | Keep the pair ≤0.1 mm apart for buried capacitance |
| Crosstalk | Return-path continuity & trace pitch | Adjacent solid plane; 3W spacing; stripline for the worst nets |
Decoupling math: two 0.1 mm-separated FR-4 planes store roughly 0.38 nF per cm². That plane capacitance has near-zero ESL, so it answers di/dt faster than any mounted 0402 capacitor can.
In practice you never guess these values. A 2D field solver — the one inside Siemens HyperLynx, Cadence Allegro's impedance engine, or Polar SI9000 — takes your layer heights, copper weights and εr and returns exact widths. For the fast serial links (PCIe, DDR, USB) you then run a 3D extraction and channel simulation in Ansys or Keysight ADS. Your fab house will also hand you a controlled-impedance stackup; always reconcile it against your solver before releasing Gerbers. For the full routing and layer-assignment workflow, see our guide to multilayer PCB design and the companion piece on controlled-impedance routing.
If you are prototyping a high-speed board and want a second set of eyes on the stackup and layer assignment, the layout team at Avecas PCB & semiconductor design services reviews controlled-impedance stackups as part of their DFM checks.
Want to design stackups like this with confidence? CourseTron's hands-on PCB & signal-integrity track walks you through real 4- and 6-layer boards, field-solver impedance targets, and EMC-clean routing. Explore the CourseTron course catalogue →
Frequently asked questions
Why is a 4-layer board so much better than a 2-layer one?
Because the signal layers sit only ~0.1 mm from a solid reference plane instead of ~1.5 mm away. That gives controllable 50 Ω impedance, a continuous low-area return path, and a buried power/ground capacitor for decoupling — none of which a 2-layer board can offer.
Does more layers always mean better signal integrity?
No. Ordering beats count. A 6-layer board that references critical signals to a split power plane will perform worse than a 4-layer board whose signals all sit against solid ground. Spend the extra layers on more reference planes, not just more routing.
Should power and ground planes be adjacent?
Yes, whenever you can. A tightly coupled PWR/GND pair (≤0.1 mm apart) acts as a high-frequency decoupling capacitor with almost no parasitic inductance, supplementing your discrete caps where they are too slow.
What tools calculate stackup impedance?
2D field solvers such as Polar SI9000, Siemens HyperLynx, and Cadence Allegro's impedance engine for trace widths; Ansys SIwave or Keysight ADS for 3D extraction and channel simulation of fast serial links.