In short: IDDQ testing measures the tiny quiescent (static) supply current a fully settled CMOS circuit draws, so that bridging, gate-oxide shorts and leakage defects — which a defect-free design should barely conduct but which raise IDDQ by orders of magnitude — are caught even when the logic still produces the correct 1s and 0s that stuck-at vectors check.
Why a logically correct chip can still be defective
A classic functional or stuck-at test asks one question: does node X hold the expected logic value? That catches a wire welded permanently to 0 or 1. But many real silicon defects do not pin a node to a rail — they add an unintended resistive path. A metal sliver bridging two adjacent signals, a pinhole in the gate oxide, or a partially-formed via can all leave a chip that still computes the right answer under nominal voltage and slow clocks, yet is one aging cycle away from failure. Stuck-at and even transition-delay patterns can walk right past these because the fault is parametric, not Boolean.
IDDQ testing attacks the problem from the power rail instead of the logic cone. It exploits a fundamental property of static CMOS: when inputs are held steady and the circuit has settled, a healthy gate conducts essentially no current between VDD and ground. Either the pull-up or the pull-down network is off, so the only current is sub-threshold and junction leakage — historically nanoamps to low microamps for a whole small block.
The physics: a defect becomes a current path
Consider a single inverter with its input held at logic 1. The NMOS is on, the PMOS is off, and the output sits at 0. No DC path exists from supply to ground — current flows only during the switching transient. Now imagine a metal bridge of, say, 500 Ω between the output and a nearby net held at 1. Suddenly there is a resistive path, and at a 1 V supply the static current jumps toward V/R ≈ 2 mA for that one site. Even a "weak" defect of tens of kΩ produces microamps — still orders of magnitude above the native leakage floor. The test simply applies vectors that put the circuit in states where the defect conducts, lets everything settle, and measures the current on VDD.
Rule of thumb: IDDQ is a defect-oriented, not fault-oriented, test. A good IDDQ vector set needs only a few dozen to a few hundred well-chosen patterns to toggle most nodes into both a 0 and 1 state, versus thousands of stuck-at patterns — because one measurement interrogates the entire die at once.
Measurement in practice and typical numbers
On the tester (Advantest or Teradyne ATE), a precision parametric measurement unit sources VDD and reads back current after a settling delay of typically 1–10 ms. Defect-free 0.5 µm and 0.35 µm parts of the 1990s measured single-digit microamps quiescent, while a bridged die read hundreds of microamps to milliamps — a crisp, unambiguous pass/fail threshold.
| Defect class | Seen by stuck-at? | Seen by IDDQ? |
|---|---|---|
| Bridging (resistive short between nets) | Only if it flips a value | Yes — strong signal |
| Gate-oxide pinhole / soft short | Often no | Yes |
| Floating / partially-open via | Sometimes | Often (if it leaves a conducting path) |
| Hard stuck-at (true open) | Yes | Not reliably |
The scaling crisis: why the leakage floor rose
IDDQ's clean separation depended on native leakage being negligible. As nodes shrank below ~130 nm, sub-threshold leakage, gate tunneling and GIDL exploded. A healthy 28 nm SoC can draw tens of milliamps of quiescent current — larger than a 1990s defect signal. The single global threshold collapsed because die-to-die process variation alone swings leakage several-fold.
Modern variants that keep IDDQ alive
- Delta-IDDQ: instead of an absolute limit, measure the difference between consecutive vectors. Process variation shifts the whole baseline up or down together, but a defect produces a sharp outlier.
- Current signatures: sort the per-vector IDDQ readings and look at the shape of the curve; a defect appears as a step discontinuity rather than a smooth ramp.
- Current-ratio / nearest-neighbour methods: normalise each die against its own population or wafer neighbours, cancelling global process drift.
- Power gating & thermal control: lowering VDD and cooling the part suppresses sub-threshold leakage so the defect signal re-emerges above the floor.
Commercial ATPG flows — Synopsys TestMAX (formerly TetraMAX), Siemens EDA Tessent, and Cadence Modus — all generate IDDQ-targeted vectors and compute IDDQ fault coverage (often via the pseudo-stuck-at model) alongside conventional stuck-at and at-speed patterns.
Where it still wins: IDDQ remains a high-value reliability screen. A gate-oxide pinhole may pass every logic test on day one yet fail after months of field stress; flagging its elevated leakage at wafer sort removes a latent reliability risk that no Boolean test can see.
How IDDQ fits with your other DFT tests
Think of IDDQ as complementary, never a replacement. A production test program layers scan-based stuck-at fault patterns for logical coverage, transition-delay (at-speed) patterns for timing defects, and an IDDQ pass to mop up resistive and leakage defects the others structurally cannot detect. Each targets a different physical failure mode, and together they drive defect-per-million rates down to the levels automotive and aerospace parts demand. Teams building these flows end-to-end often lean on hands-on training such as ChipXpert's VLSI DFT programs to connect the fault models to real ATPG runs.
Want to run TestMAX and Tessent IDDQ flows on real netlists and read live current signatures? Explore CourseTron's hands-on Design-for-Test track at /courses.
Frequently asked questions
Is IDDQ testing obsolete at advanced nodes?
Not obsolete, but transformed. Absolute-threshold IDDQ died below ~130 nm because native leakage swamped the defect signal. Statistical variants — delta-IDDQ, current signatures and neighbour-normalised limits — keep it useful, and it is still widely applied as a reliability screen at wafer sort for high-dependability parts.
How many IDDQ vectors do I need?
Far fewer than stuck-at — typically tens to a few hundred patterns. Each measurement interrogates the whole die at once, so the goal is only to toggle most nodes to both logic states (good "node toggle" coverage) so any latent bridge is placed in a conducting condition at least once.
What is the pseudo-stuck-at fault model?
It is the fault model ATPG tools use to grade IDDQ coverage. A node is considered covered if a vector both drives it to a value and makes any defect at that node draw measurable current, bridging the gap between the abstract stuck-at model and the physical leakage mechanism IDDQ actually senses.
Does IDDQ detect open (break) defects?
Generally no. An open leaves a node floating or disconnected rather than opening a VDD-to-GND path, so quiescent current does not rise. Opens are better caught by stuck-at or transition tests — which is exactly why the three test types are run together.