In short: The transition (delay) fault model targets timing defects by modelling each node as either slow-to-rise or slow-to-fall, and detects them with an at-speed two-pattern test that first initialises the node and then launches a transition captured within one functional clock period.
Stuck-at testing catches a huge share of manufacturing defects, but it is a static model: it asks only whether a node can be driven to 0 and to 1. Modern silicon fails in subtler ways. A resistive via, a partially-formed contact, or a slightly-too-long wire may still settle to the correct logic value — just not within the clock period. These timing defects pass a slow functional test and a stuck-at test, yet cause the part to fail in the customer's system at rated frequency. The transition fault model exists precisely to screen them.
What a transition fault actually is
The transition fault model places two faults at every circuit node, mirroring the two stuck-at faults:
- Slow-to-rise (STR): the node is slow making a 0→1 transition. The rising edge arrives later than the clock allows.
- Slow-to-fall (STF): the node is slow making a 1→0 transition.
A design with N stuck-at fault sites therefore has roughly 2N transition fault sites — one STR and one STF per location. The model assumes a "gross delay": the extra delay is large enough that any path through the faulty node will be slow. This is a simplification (contrast the path-delay fault model, which targets accumulated delay along specific critical paths), but it makes test generation tractable while still catching the majority of localised timing failures.
Key fact: A transition fault needs two vectors to detect, not one. V1 sets the node to the starting value; V2 launches the opposite transition and the result is captured one clock later. Detecting an STR fault requires creating a rising transition at that node and propagating it to an observable point — exactly like detecting the node stuck-at-0, but under a timing constraint.
Why two patterns and why "at-speed"
Consider detecting slow-to-rise on net n. V1 must force n = 0. V2 must force n = 1 and simultaneously create a sensitised path from n to a flop or primary output. The two vectors are applied back-to-back; the capture clock after V2 runs at the functional (rated) period. If the 0→1 edge does not reach the capture flop before that edge, the flop latches the old value and the fault is observed as a mismatch. Apply the same vectors with a slow clock and the edge always makes it — which is why delay faults demand at-speed capture.
Launch-off-capture vs launch-off-shift
Scan-based at-speed testing delivers the V1→V2 pair in one of two ways, and the choice shapes both coverage and tester cost:
| Method | How V2 is launched | Trade-off |
|---|---|---|
| Launch-off-shift (LOS / skewed-load) | Last scan-shift edge launches the transition, then capture | Higher coverage, but the fast shift→capture gap stresses scan-enable timing |
| Launch-off-capture (LOC / broadside) | First functional capture produces V2 from V1 through the logic | Easier scan-enable timing; V2 is not freely controllable, so ATPG works harder |
In practice most production flows use LOC because scan-enable does not need to switch at speed. Synopsys TetraMAX/TestMAX, Siemens EDA Tessent, and Cadence Modus all generate both styles; you pick per the DFT clocking architecture.
Coverage numbers and interview reality
A well-structured scan design reaches 98–99% stuck-at coverage but typically only 80–92% transition fault coverage. The gap comes from untestable transitions: a node may be slow-to-rise, but if no two-pattern sequence can both set it low and launch a propagating rising edge at speed, the fault is ATPG-untestable. False paths and multicycle paths further reduce the testable set, which is why accurate SDC timing exceptions are fed to the ATPG tool.
Key fact: Transition pattern counts are often 2–3× the stuck-at pattern count for the same block, because each fault needs an initialisation vector plus a launch vector. This directly drives tester memory and test time — a real cost-of-test lever in high-volume parts.
Where transition faults fit in the test flow
- Static timing & constraints: SDC false/multicycle paths are exported so ATPG does not waste effort on untestable transitions.
- Scan insertion: at-speed clocking (OCC — on-chip clock controllers, fast PLL-driven capture) is built in.
- ATPG: transition patterns are generated, usually after stuck-at, often reusing scan loads via n-detect or embedded compression.
- Pattern grading: small-delay-defect (SDD) metrics rank patterns by how tight a timing slack they exercise, improving quality beyond gross-delay coverage.
Teams building full RTL-to-GDS DFT competence usually pair this with hands-on ATPG labs — the kind of structured training offered by ChipXpert's VLSI programs — so engineers see pattern counts and coverage move in a real tool. If you are coming from a foundations background, start with the stuck-at fault model before diving into two-pattern delay testing.
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Frequently asked questions
How is a transition fault different from a stuck-at fault?
A stuck-at fault is static — it asks whether a node can be set to 0 or 1 with a single vector. A transition fault is dynamic: it asks whether the node can change value fast enough, so it needs a two-vector sequence applied at the rated clock speed.
Why does transition coverage lag stuck-at coverage?
Many transitions are ATPG-untestable because no at-speed two-pattern sequence can both initialise and launch a propagating edge, and false/multicycle paths must be excluded. This commonly leaves transition coverage in the 80–92% range versus 98%+ for stuck-at.
What is the difference between launch-off-shift and launch-off-capture?
LOS launches the transition from the final scan-shift clock edge (higher coverage, but scan-enable must switch at speed). LOC launches it from the first functional capture through the logic (easier timing, harder ATPG). LOC is more common in production.
Does the transition fault model catch small delay defects?
The basic gross-delay assumption catches large localised delays. Catching small delay defects (SDD) needs timing-aware ATPG that launches transitions through the longest paths, graded by timing slack — a feature in modern Tessent, TestMAX and Modus flows.
References & Further Reading
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