Parametric testing

In short: Parametric testing measures a device's electrical characteristics — supply currents, pin voltages, leakage, continuity and the minimum/maximum operating voltages — against datasheet limits before any functional pattern runs, so that electrically broken or out-of-spec parts are screened out cheaply and safely.

When a freshly fabricated die lands on an Automatic Test Equipment (ATE) tester, the very first thing the program does is not run millions of logic vectors. It checks whether the part is even electrically alive and within spec. That stage is parametric testing, and understanding it is a staple of post-silicon and product-engineering interviews.

What parametric testing actually measures

Parametric tests force a known stimulus (a voltage or a current) and measure the resulting response, comparing it to a numeric pass/fail window. They fall into two families. DC parametrics cover static quantities — pin continuity, input/output leakage (IIL/IIH, IOZ), drive levels (VOL/VOH, VIL/VIH), and supply currents (IDD static, IDDQ quiescent). AC parametrics cover timing-related quantities — rise/fall times, propagation delay (tPD), setup/hold, and output slew — measured with the tester's timing engine rather than a simple meter.

Order matters: continuity → leakage → power/Vmin/Vmax → functional. You never apply a full 1.2 V core rail to a part whose VDD-to-VSS path might be shorted. The sequence is a safety ladder, not just a convention.

Continuity: is every pin bonded?

Continuity (the "open/short" or contact test) confirms that the tester channel actually reaches silicon through the probe needle or socket pin and the bond wire. The classic method forces a small current (typically ±100 µA) into the pin while all supplies are at 0 V, and measures the voltage across the ESD protection diode to VSS or VDD. A healthy pin clamps at roughly 0.5–0.7 V (one diode drop). An open rails to the compliance limit; a short sits near 0 V. Fail here and nothing else is trustworthy — so continuity runs first, before power is ever applied.

Leakage: how much current leaks when it shouldn't

With supplies now applied, leakage tests force a pin to VDD or VSS and measure the tiny current that flows. Input leakage (IIH/IIL) on a CMOS gate should be in the nanoampere range; a few microamps signals gate-oxide damage or ESD latent failure. IDDQ (quiescent supply current) is the most powerful leakage screen: in a static CMOS circuit, a defect-free die at rest draws almost no current (µA), so a vector that leaves the part in a known state and then measures an IDDQ spike of, say, 2 mA exposes bridging shorts that logic tests can miss entirely.

Vmin and Vmax: the voltage operating window

Vmin is the lowest supply voltage at which the part still passes a reference pattern; Vmax is the highest it survives without failing. Engineering characterization sweeps VDD in fine steps (e.g. 0.6 V → 1.1 V in 10 mV increments) and plots a shmoo — a 2-D pass/fail map of voltage vs. frequency. A part specced at 1.0 V might hold Vmin = 0.82 V; the margin between that and the datasheet point is the guard band against aging and temperature. Vmin screening weeds out slow, leaky corners; Vmax protects against latch-up and oxide stress.

Why parametrics come before functional test

Three reasons. Safety: you never stress a part whose rails might be shorted — a short at 1.2 V can vaporize a bond wire or the probe card. Economy: functional/scan patterns are the longest and most expensive part of the test program; screening gross electrical failures first saves tester seconds that dominate cost of test. Diagnosis: a continuity or leakage failure points at a physical defect (open bond, bridging short, ESD damage) far more directly than a functional miscompare, which could be any of millions of nodes.

On modern ATE from Advantest (V93000) and Teradyne (UltraFLEX), parametric measurements use a per-pin PMU (Parametric Measurement Unit) that can be a force-voltage/measure-current (FVMI) or force-current/measure-voltage (FIMV) source. The same PMU hardware runs continuity, leakage and VOL/VOH.

Where parametric data feeds back

Parametric results are not just pass/fail — the measured values stream into the STDF datalog, where product and yield engineers build distributions. Shifts in IDDQ or Vmin across a lot flag process drift at the fab long before functional yield moves. This is the bridge between test-floor data and design-for-test strategy, and it is exactly the kind of closed-loop thinking that a silicon design-services team like Avecas relies on when debugging first-silicon bring-up.

Want hands-on with ATE programs and shmoo plots? CourseTron's post-silicon validation track walks you through writing a real parametric test suite on an emulated tester. Explore it on our courses page.

Frequently asked questions

Is IDDQ a DC or AC parametric test?

IDDQ is a DC parametric test — it measures a static supply current. However, it requires a functional vector to first place the circuit in a defined quiescent state, so it sits at the boundary and is often run interleaved with scan patterns.

What is the difference between Vmin and setup/hold timing?

Vmin is a DC/operating-window parameter (lowest working supply voltage). Setup and hold are AC parameters measured by the tester's timing edges. A part can pass Vmin yet fail hold timing at a given frequency, which is why shmoo plots sweep both voltage and frequency.

Why force current for continuity instead of voltage?

Forcing a small, current-limited stimulus guarantees you cannot damage the pin if it is shorted, and the diode's I–V curve makes the open/short decision unambiguous from the measured clamp voltage.

Can functional test replace parametric test?

No. Functional test verifies logical behavior but can be blind to resistive shorts, elevated leakage, or marginal drive strength that still "works" at nominal conditions. Parametrics and IDDQ catch physical defects that functional vectors miss.

Once a die clears every parametric gate, the program hands off to the structural and functional stages — see our companion piece on scan chain testing for what happens next.