In short: Insertion loss (S21) tells you how much of your signal survives the trip down a PCB channel, and return loss (S11) tells you how much bounces back off impedance discontinuities — together they are the two dB budgets every high-speed serial link must satisfy, and you measure both with a VNA or extract them from TDR/field solver data.
When a 10 Gbps bit leaves a SerDes transmitter, it does not arrive at the receiver unchanged. The copper trace, the vias, the connector, and the package all conspire to attenuate, reflect, and smear the waveform. S-parameters are the language engineers use to quantify exactly that. Of the four parameters in a two-port network, two dominate signal-integrity (SI) work: insertion loss and return loss. Master these two and you can read a channel report the way a cardiologist reads an ECG.
What S-parameters actually describe
A scattering parameter Sij is the ratio of the wave coming out of port i to the wave going in at port j, with every other port terminated in the reference impedance (almost always 50 Ω single-ended, 100 Ω differential). They are complex numbers — magnitude and phase versus frequency — but SI engineers usually plot magnitude in decibels first.
- S11 (return loss): wave reflected back to the source port. Caused by impedance mismatches — a trace that drops to 42 Ω over a plane split, a via stub, a connector footprint.
- S21 (insertion loss): wave transmitted to the far port. Combines conductor (skin-effect) loss, dielectric (tan δ) loss, and any energy lost to reflections.
- S22 / S12: the mirror-image reflection and reverse transmission; for a passive, reciprocal channel S12 = S21.
Sign convention trap: insertion loss of a passive channel is a negative dB number (e.g. S21 = −12 dB), but datasheets often quote "insertion loss = 12 dB" as a positive magnitude. Return loss is reported as a positive number too (RL = −S11 dB), where bigger is better — 20 dB return loss is far cleaner than 8 dB.
Where the loss comes from
Insertion loss on a PCB is not a single mechanism. At low frequency, DC resistance dominates. As frequency climbs, two effects take over and both scale with frequency:
- Conductor loss grows with √f because of the skin effect — current crowds into the outer skin of the copper, shrinking the effective cross-section. This is why surface roughness of the copper foil (quantified by a Huray or Hammerstad model) matters so much above 10 GHz.
- Dielectric loss grows linearly with f and is set by the laminate's loss tangent (tan δ). Standard FR-4 has tan δ ≈ 0.02; low-loss materials like Megtron 6 or Tachyon sit near 0.002 — a 10× improvement that directly buys channel reach.
A practical rule for a 6-inch stripline on FR-4: expect roughly 1 dB of insertion loss per inch at the 5 GHz Nyquist of a 10 Gbps NRZ link, so about 6 dB total. On Megtron 6 the same trace might lose under 3 dB. That difference decides whether your receiver's CTLE/DFE can recover the eye — which ties directly into eye-diagram and jitter analysis.
The dB budget: how much is allowed
Serial standards publish an insertion-loss budget at the Nyquist frequency (half the bit rate). The receiver equalizer can only claw back so much, so the channel must land under the limit.
| Standard | Bit rate | Nyquist | Typical IL budget @ Nyquist |
|---|---|---|---|
| PCIe 4.0 | 16 GT/s | 8 GHz | ~28 dB (end-to-end) |
| PCIe 5.0 | 32 GT/s | 16 GHz | ~36 dB |
| USB 3.2 Gen2 | 10 Gbps | 5 GHz | ~−12 dB channel |
| 112G PAM4 (OIF-CEI) | 112 Gbps | 28 GHz | ~30 dB (very low-loss mandatory) |
For return loss, most high-speed specs want better than 10 dB up to the Nyquist (some tighten to 15–20 dB at low frequency). A single via stub resonance can punch a −6 dB notch into S11 at a few GHz and fail the mask even when average loss looks fine — which is why back-drilling via stubs is routine on PCIe 5/112G boards.
Measuring it: VNA and TDR
The gold-standard instrument is a Vector Network Analyzer (VNA). You calibrate out the test fixtures (SOLT or TRL calibration moves the reference plane to the DUT), sweep frequency, and read S11/S21 directly. For differential pairs you capture a 4-port measurement and convert to mixed-mode parameters (SDD21 = differential insertion loss, SDD11 = differential return loss) using the standard mixed-mode transform.
A Time-Domain Reflectometer (TDR) is the complementary view: it launches a fast step and shows impedance versus distance, so you can literally see where a reflection occurs — the connector, a via, the BGA breakout. VNA and TDR data are mathematically linked by the Fourier transform, and modern tools let you toggle between them.
In simulation, you rarely touch hardware first. A 3D full-wave solver — Ansys HFSS, Cadence Clarity, or Siemens HyperLynx — extracts a Touchstone (.s4p) model of the channel, which you then drive through a statistical or transient SerDes simulation in tools like Cadence Sigrity or Keysight ADS. The extracted S-parameters must be passive, causal, and reciprocal; a non-passive model (|S|>1 somewhere) will blow up a time-domain sim, so quality checks come first. Teams building these flows from scratch often lean on specialist high-speed PCB and SI design services to validate the stackup before fab.
Reading a real channel report
Put it together with a worked example. Suppose a PCIe 5.0 lane extraction shows SDD21 = −32 dB and SDD11 = −9 dB at 16 GHz. The insertion loss is within the ~36 dB end-to-end budget — good. But return loss at −9 dB is just shy of the 10 dB target, and a plot reveals a sharp notch at 12 GHz: a classic via-stub resonance. The fix is not more equalization (that cannot help reflections); it is a layout change — back-drill the stub, tune the antipad, or adjust the breakout — then re-extract and re-check. This loop between measurement, physical cause, and layout fix is the daily reality of SI engineering, and it is exactly what we drill in the high-speed channel design module.
Want to go from reading S-parameter plots to running full-wave extractions and SerDes compliance sims yourself? The CourseTron Signal Integrity & High-Speed PCB course walks you through VNA measurement, Touchstone QA, and eye-closure analysis on real boards.
Frequently asked questions
Is insertion loss the same as attenuation?
Not quite. Attenuation usually means only the energy dissipated in the conductor and dielectric. Insertion loss (S21) includes that plus energy lost to reflections from impedance mismatches, so on a poorly matched channel insertion loss can be worse than pure attenuation.
Why is good return loss a large positive dB number?
Return loss is defined as the negative of S11 in dB. A reflection coefficient of 0.1 gives S11 = −20 dB, so return loss = 20 dB, meaning only 1% of power bounced back. Higher return loss = less reflection = cleaner impedance.
Can equalization fix bad return loss?
No. CTLE, FFE and DFE compensate for insertion-loss roll-off (frequency-dependent attenuation), but reflections create echoes and resonant notches that equalizers cannot remove. Return-loss problems must be fixed physically — stackup, via design, connector launch.
What file format carries S-parameters?
Touchstone files: .s2p for a single-ended two-port, .s4p for a differential pair (four ports). They list frequency with real/imaginary or magnitude/angle for every S-parameter and are read by every major SI tool.