In short: An eye diagram overlays thousands of unit-interval bit transitions so you can read signal integrity at a glance — a wide-open "eye" means healthy margin, while jitter (the horizontal eye closure) splits into deterministic components you can bound and random components that must be extrapolated to a bit-error-rate target.
What an eye diagram actually shows
When a multi-gigabit serial link toggles between logic levels, every bit occupies one unit interval (UI) — for a 10 Gb/s PCIe or SerDes lane that UI is 100 ps. An eye diagram is built by chopping the captured waveform into one-UI (or two-UI) slices and superimposing them on a common time axis. After a few thousand overlaid transitions, the rising and falling edges trace out the characteristic "eye" shape. The open region in the center is the window where a receiver can safely sample and recover the correct logic value.
Two measurements dominate. Vertical eye opening (in millivolts) is the noise and amplitude margin — how much the voltage can droop from reflections, crosstalk and loss before the slicer guesses wrong. Horizontal eye opening (in picoseconds, or as a fraction of the UI) is the timing margin, and it is set almost entirely by jitter. A 100 ps UI that collapses to 55 ps of usable eye width means 45 ps has been eaten by jitter and ISI.
The eye mask: pass or fail in one shape
Standards bodies don't ask you to interpret an eye subjectively. They publish an eye mask — typically a hexagon or diamond centered in the eye plus two bars at the top and bottom rails. The rule is brutally simple: no trace sample may fall inside the mask. If even one of the overlaid transitions intrudes into the forbidden region, the link fails compliance. USB 3.2, PCIe (via the PCI-SIG compliance program), SATA and the various 802.3 Ethernet clauses each define their own mask geometry at the relevant test point.
A compliance mask converts millions of waveform samples into a single verdict. On a Keysight or Tektronix real-time scope, mask hits are counted automatically and reported as a hit ratio — zero hits over the required sample population is the pass condition.
Deterministic vs random jitter
Jitter is the deviation of signal edges from their ideal UI boundaries, and the single most important idea in high-speed SI is that total jitter is not one number. It decomposes into two families with completely different statistics:
- Deterministic jitter (DJ) is bounded and repeatable. It has a peak-to-peak value that does not grow with observation time. Its sub-components include inter-symbol interference (ISI) from channel loss and reflections, duty-cycle distortion (DCD) from asymmetric rise/fall or a skewed threshold, and periodic jitter (PJ) from coupled clocks or switching-regulator ripple.
- Random jitter (RJ) comes from thermal and shot noise. It is unbounded and Gaussian, characterized by an RMS value (one sigma) rather than a peak-to-peak value. Because a Gaussian tail never truly ends, RJ peak-to-peak only has meaning once you fix a probability — i.e., a target bit-error rate.
This split is why you cannot just read "total jitter" off a histogram and declare victory. The measured histogram at a modest capture only shows the DJ and the inner part of the RJ distribution. The rare large excursions that actually cause bit errors live out in the Gaussian tails you never captured directly.
Separating the components: the jitter budget
Modern scopes and the analysis software that ships with them (Keysight's EZJIT, Tektronix DPOJET, or the jitter engines in Synopsys and Cadence simulation flows) perform jitter separation. The workflow is roughly: measure the time-interval-error (TIE) track, separate periodic and data-dependent contributions in the frequency domain, fit the uncorrelated residual to a dual-Dirac + Gaussian model, then convolve everything to predict total jitter at the target BER.
The key relationship engineers memorize for interviews is the dual-Dirac extrapolation:
TJ(BER) = DJ(δδ) + 2 · Q(BER) · RJ(rms). For a 1e-12 BER, Q ≈ 7.03, so random jitter is multiplied by about 14 before being added to deterministic jitter.
That multiplier is the whole point. A link with 2 ps RMS of random jitter contributes roughly 28 ps of peak-to-peak jitter at 1e-12 — a huge slice of a 100 ps UI — even though its histogram looked tight at 2 ps sigma.
| Component | Family | Typical source | Metric |
|---|---|---|---|
| ISI | Deterministic (DDJ) | Channel loss, reflections | pk-pk ps |
| DCD | Deterministic | Threshold / slew asymmetry | pk-pk ps |
| PJ | Deterministic | SMPS ripple, clock coupling | pk-pk ps |
| RJ | Random | Thermal / shot noise | RMS (σ) ps |
Fixing a closing eye in practice
When an eye fails, the jitter decomposition tells you where to aim. Heavy ISI (data-dependent jitter) points at channel loss, so you reach for equalization — transmitter FFE pre-emphasis and receiver CTLE/DFE. A strong periodic spur at your DC-DC converter's switching frequency says route power away from the lane or add filtering. A large RJ floor usually means a noisy reference clock or PLL and no amount of equalization will help. Simulating these fixes before board spin — IBIS-AMI models driven through an S-parameter channel in Cadence Sigrity or Keysight ADS — is now standard practice, and it is exactly the kind of correlation work Avecas offers as a high-speed design service for teams taping out their own interconnect.
Want to go from reading an eye to budgeting and closing one on real hardware? Our CourseTron high-speed signal integrity course walks through live scope captures, mask testing and jitter separation end to end.
How this connects to the wider link
Eye diagrams are the diagnostic lens, but they sit inside a larger serial-link story. If the terms "UI", "FFE" and "CTLE" above were new, start with our SerDes basics primer, then come back here. And because almost all eye closure in long channels is loss-driven, the companion read on channel loss and equalization shows how to recover margin you thought was gone. For training that pairs this theory with lab time, teams also look at ChipXpert's VLSI and SI training tracks.
FAQ
Why does the eye close horizontally but not vertically on long traces?
Dielectric and copper loss attenuate high-frequency content, which slows edge rates and spreads energy into neighboring bits (ISI). That smears edge timing — closing the eye horizontally — before it meaningfully reduces the steady-state voltage rails, so timing margin disappears first.
Can I just measure total jitter instead of separating DJ and RJ?
No. Peak-to-peak total jitter depends on how long you observe, because the unbounded random component keeps producing rarer, larger excursions. Only by separating the bounded DJ from the Gaussian RJ can you extrapolate a meaningful total jitter at a fixed BER like 1e-12.
What does "dual-Dirac" mean?
It is a simplified model that represents all deterministic jitter as two delta functions (Diracs) separated by DJ(δδ), each convolved with the same Gaussian for random jitter. It intentionally over-bounds reality a little, giving a conservative, standards-friendly total-jitter estimate.
Which tools generate compliance eye diagrams?
On hardware, Keysight and Tektronix real-time scopes with EZJIT/DPOJET. In simulation, Synopsys HSPICE/StatEye-style flows, Cadence Sigrity, and Keysight ADS driving IBIS-AMI models through measured or simulated channels.