In short: A SerDes converts wide, slow parallel buses into one or a few high-speed serial lanes, then recovers the clock from the data itself (CDR) and undoes channel loss with equalization (CTLE, FFE, DFE) so the eye diagram reopens at the receiver.
Every modern interface that moves real bandwidth, from PCIe and USB to 400G Ethernet and HBM, is built on a SerDes, short for Serializer/Deserializer. If you are preparing for a high-speed I/O or physical-design interview, this is one of the highest-leverage topics you can master, because the same five ideas, serialization, CDR, equalization, the eye diagram, and lanes, recur across every standard.
Why serialize at all?
A naive engineer asks: why not just run 128 parallel wires? The answer is skew, cost, and pins. At multi-gigabit rates, bit periods shrink below the picosecond-scale mismatch between traces, so parallel buses fall apart from skew. Serializing trades width for speed: one differential pair carrying 32 Gb/s replaces a 32-bit bus at 1 Gb/s, cutting package pins, connector size, and board area dramatically.
Concretely, a 32:1 serializer takes 32 parallel bits clocked at, say, 1 GHz and shifts them out of one lane at 32 GHz (a 32 Gb/s line rate). A PLL multiplies the reference clock up to the bit clock, and a multiplexer tree (often 2:1 stages) does the final speed-up. The data is usually encoded, 8b/10b in older standards or 128b/130b in PCIe Gen3+, to guarantee enough transitions for the receiver's clock recovery and to keep the signal DC-balanced.
Clock and data recovery (CDR)
The lane carries no separate clock, that would defeat the whole point. The receiver must regenerate the sampling clock from transitions in the data. This is CDR. The dominant architecture is a phase-locked loop whose phase detector, commonly a Bang-Bang (Alexander) type, nudges the local clock early or late to center its sampling point in each bit.
Key fact: CDR needs transitions to lock. Standards enforce a maximum run length (consecutive identical bits) via line coding or scrambling so the loop never loses its phase reference during a long string of 1s or 0s.
Two knobs dominate CDR design: loop bandwidth (how fast it tracks jitter) and jitter tolerance (how much input jitter it can swallow before bit errors). A loop that tracks fast also passes high-frequency jitter to the sampler, so there is always a trade-off you should be ready to discuss.
Why equalization is unavoidable
Copper channels act as low-pass filters. A 25 Gb/s signal over 30 dB of insertion loss arrives as a smeared mess where each bit bleeds energy into its neighbors, this is inter-symbol interference (ISI). Equalization reshapes the response to flatten the channel. Three techniques cover almost every interview question:
| Technique | Where | What it does | Noise penalty |
|---|---|---|---|
| FFE (Feed-Forward) | TX (pre-emphasis) or RX | Linear FIR filter; boosts high-frequency content before loss | Amplifies noise / reduces swing |
| CTLE | RX analog front-end | Peaking amplifier that boosts the band near Nyquist | Amplifies noise with signal |
| DFE (Decision-Feedback) | RX | Subtracts post-cursor ISI using already-decided bits | None (nonlinear); but error propagation risk |
A real link stacks them: TX FFE pre-distorts, RX CTLE provides coarse continuous-time peaking, and a multi-tap DFE cleans residual post-cursor ISI. Because the DFE uses decided bits, it adds no noise, which is its superpower, but a wrong decision can propagate, so it cannot fix the pre-cursor or the first post-cursor tap as cheaply as people assume.
Reading the eye diagram
The eye diagram overlays many unit intervals of the received signal on one time axis. The open region, the "eye," is where the sampler can safely decide. Eye height (vertical opening) is voltage margin against noise; eye width (horizontal opening) is timing margin against jitter. A closed eye means the receiver cannot reliably distinguish 1 from 0.
Key fact: For PAM4 signaling (used in 100G-per-lane Ethernet and PCIe 6.0), there are three stacked eyes instead of one, so each eye is about one-third the height of an NRZ eye, which is exactly why PAM4 links lean so heavily on strong DFE and forward error correction.
Engineers simulate eyes with statistical and time-domain tools such as Cadence Sigrity and the IBIS-AMI flow, and measure them on real silicon with high-bandwidth sampling scopes. Compliance masks, forbidden regions the trace must not enter, come straight from the standard.
Lanes, link training, and bonding
One lane rarely suffices. A PCIe x16 slot bonds 16 independent lanes, each with its own SerDes, CDR, and equalizer. At link bring-up, the two ends run link training: they negotiate speed, then adapt TX FFE and RX equalizer coefficients by exchanging training sequences until the eye is open on every lane. Lanes are then deskewed and striped so the aggregate payload reassembles in order. For the handshake and layering that sit on top of this physical layer, see our companion piece on PCIe protocol basics, and for the signaling trade-offs between two- and four-level modulation, read PAM4 vs NRZ signaling.
These same building blocks underpin the design-services work done by teams like Avecas VLSI design services, where high-speed I/O integration is a routine part of SoC tapeouts.
Want to go from eye diagrams to real link bring-up? CourseTron's high-speed I/O and protocols track walks you through CDR, adaptive equalization, and PCIe/Ethernet PHY design with hands-on labs. Browse the CourseTron courses →
Frequently asked questions
What is the difference between FFE and DFE?
FFE is a linear FIR filter that boosts high frequencies, but it amplifies noise along with the signal. DFE is nonlinear: it subtracts post-cursor ISI using bits the receiver has already decided, so it adds no noise, at the cost of possible error propagation.
Why does a SerDes need line coding like 8b/10b?
Line coding guarantees frequent transitions and DC balance. The CDR relies on transitions to recover the clock, and a bounded run length keeps it locked even through long runs of identical bits.
What does a closed eye mean?
It means ISI, jitter, and noise have eroded the voltage and timing margins so much that the sampler can no longer reliably separate logic levels, the bit error rate explodes. Equalization and CDR exist to reopen it.
Why is PAM4 harder than NRZ?
PAM4 packs two bits per symbol in four voltage levels, tripling throughput for the same baud rate, but it splits one eye into three smaller ones, cutting noise margin roughly 3x and demanding stronger equalization plus FEC.