In short: PCIe (PCI Express) is a high-speed, point-to-point serial interconnect that links CPUs to GPUs, SSDs, and network cards using independent lanes that scale from x1 to x16. It is built as a three-layer stack — Transaction, Data Link, and Physical — that moves data in packets called TLPs, and each new generation roughly doubles the per-lane bandwidth.
PCIe, short for Peripheral Component Interconnect Express, is the dominant expansion interconnect inside nearly every modern computer. It replaced the older parallel PCI and AGP buses with a serial, point-to-point design: instead of many devices sharing one wide parallel bus, each device gets its own dedicated connection to a central switch fabric rooted at the CPU or chipset.
This shift matters because parallel buses hit a wall — keeping dozens of wires perfectly synchronized ("skew") becomes impossible at high clock rates. A serial link sends bits one after another on a differential pair, embeds the clock in the data stream, and sidesteps the skew problem entirely. The result is an interconnect that has scaled from 2.5 GT/s in 2003 to 64 GT/s today while keeping the same software programming model.
The building block of PCIe is the lane. A lane is a single bidirectional serial channel. Bundling lanes together forms a link, written as x1, x2, x4, x8, or x16, where the number is the lane count. A graphics card typically uses a x16 link; an NVMe SSD commonly uses x4.
Data striping spreads bytes across the available lanes, so a x16 link delivers roughly sixteen times the throughput of a single lane. Links are negotiated at startup — a x16 card in a x8 slot will train down to x8 rather than fail.
PCIe organizes its work into three stacked layers, each with a clean job. Understanding them is the key to understanding how a memory read becomes electrical signals and back again.
The top layer creates and consumes Transaction Layer Packets (TLPs). A TLP carries a request or completion — a memory read, a memory write, an I/O access, or a configuration access. It holds the address, the payload, routing information, and attributes. This layer also manages flow control using a credit system, so a sender never overruns a receiver's buffers.
The middle layer guarantees reliable delivery between two directly connected devices. It wraps each TLP with a sequence number and a LCRC checksum, and uses an Ack/Nak protocol: a corrupted TLP is detected and automatically retransmitted. It also generates small DLLPs (Data Link Layer Packets) for acknowledgements and flow-control credit updates.
The bottom layer turns packets into bits on the wire. It handles 128b/130b encoding (Gen3 onward), scrambling, lane striping, differential signalling, and the link-training state machine that negotiates speed and width at power-up.
Each PCIe generation has roughly doubled the raw per-lane transfer rate. "GT/s" means gigatransfers per second; after encoding overhead you get the usable byte rate. Gen1 and Gen2 use inefficient 8b/10b encoding (20% overhead), while Gen3 onward switched to 128b/130b (about 1.5% overhead), which is why Gen3's effective rate more than doubled Gen2's.
A full PCIe 5.0 x16 link therefore delivers roughly 63 GB/s in each direction — enough to feed a modern AI accelerator. Generations are backward and forward compatible: a Gen5 card works in a Gen3 slot, simply running at the lower common speed.
Suppose a GPU needs to read system memory. The sequence is worth tracing:
Because requests and completions are split rather than blocking, PCIe can keep many transactions in flight at once — a property called split-transaction or non-posted traffic — which is central to its high throughput.
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Explore CourseTron Courses →The physical slots are one expression of PCIe, but the protocol also runs over M.2 connectors, U.2 cables, and backplanes in servers. The connector shape differs; the three-layer protocol underneath is the same.
A lane is a single serial channel (one transmit pair plus one receive pair). A link is a group of lanes negotiated to work together, such as x4 or x16. More lanes mean proportionally more bandwidth.
Yes. PCIe is both backward and forward compatible. The two devices train to the highest speed and widest lane count they both support, so a Gen5 SSD runs fine (just slower) in a Gen3 slot.
8b/10b spends 2 of every 10 bits on encoding, a 20% tax on bandwidth. From Gen3, PCIe adopted 128b/130b, cutting the overhead to about 1.5% and letting the usable rate more than double even though the raw rate only went from 5 to 8 GT/s.
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