In short: The ddr protocol is the command-and-timing language a CPU's memory controller uses to talk to DRAM chips, which are organized as banks of rows and columns. Its signature trick is transferring two data words per clock cycle (double data rate) by latching data on both the rising and falling clock edges. LPDDR is a low-power cousin of standard DDR, tuned for phones and laptops rather than servers.
DDR stands for Double Data Rate, and the ddr protocol defines how a memory controller issues commands to DRAM (Dynamic Random-Access Memory) and how data moves back and forth across the bus. DRAM stores each bit as a charge on a tiny capacitor paired with an access transistor. Because that charge leaks away, the memory must be periodically refreshed — the "dynamic" in the name. The protocol is a strict, clocked handshake: the controller drives address and command pins, the DRAM responds within fixed timing windows, and both sides must agree on a published set of timing parameters.
Modern standards (DDR4, DDR5) are defined by JEDEC. Every generation raises data rates and tightens efficiency, but the core organization — banks, rows, columns, and a small vocabulary of commands — has stayed remarkably consistent since the first DDR SDRAM.
Inside a DRAM chip, the storage array is a grid. To read or write one location the controller must address three things in order:
A typical access is ACTIVATE → READ/WRITE → PRECHARGE. If the next access hits the same open row ("row hit"), the controller skips straight to another column command — fast and efficient. A "row miss" forces a PRECHARGE and a fresh ACTIVATE, which costs latency. Good memory controllers reorder requests to maximize row hits and keep banks busy in parallel.
Earlier SDRAM moved one data word per clock cycle, on the rising edge only. DDR latches data on both edges of the clock, doubling throughput without doubling the clock frequency (which would cost power and worsen signal integrity). Commands and addresses still use single data rate — one edge — because they do not need the bandwidth and benefit from timing margin.
To feed those edges, DDR uses prefetch: each internal array access fetches a fixed burst. DDR4 uses an 8n prefetch (burst length 8), so one column command streams eight words back to back. DDR5 moves to 16n prefetch and splits each channel into two independent sub-channels, improving concurrency.
The ddr protocol is governed by named timings, usually quoted as a set like CL-tRCD-tRP-tRAS:
Standard DDR (DDR4/DDR5 DIMMs) targets desktops and servers: it prizes raw bandwidth and capacity, uses a wide 64-bit channel per module, and tolerates higher power. LPDDR (Low-Power DDR) is built for battery devices — phones, tablets, thin laptops — and is soldered directly to the board rather than socketed.
The underlying ideas — banks, rows, columns, ACTIVATE/READ/WRITE/PRECHARGE, refresh, and double-edge transfers — are shared. LPDDR simply re-tunes the same ddr protocol concepts for a power budget measured in milliwatts.
Real projects and industry tool flows, with certification.
Explore CourseTron Courses →No. The clock frequency is unchanged; DDR transfers data on both the rising and falling edge, so each clock carries two words. A 1600 MHz clock therefore reaches 3200 MT/s.
Each bit is a charge on a leaky capacitor. Without a periodic REFRESH command the charge decays and data is lost, so the controller refreshes every row within a fixed window (commonly 64 ms, tightened at high temperature).
If the next access targets a row already open in the sense amplifiers, the controller issues only a column command — skipping PRECHARGE and ACTIVATE. That saves tRP + tRCD of latency, which is why controllers reorder requests to favor row hits.
Not necessarily. LPDDR5/5X can match or exceed desktop DDR data rates per pin; it is optimized for low voltage and idle power, with narrower, soldered channels rather than socketed modules.
Related: PCIe protocol basics · Glossary · all courses.