In short: A 4-layer board is the cheapest honest stackup that still gives you continuous reference planes, but the moment you need two uninterrupted ground references around your fast signals, controlled impedance you can actually route, or a quiet power delivery network, a 6-layer stackup earns its ~20–40% extra fab cost.
The jump from two layers to four is a correctness fix; the jump from four to six is an engineering decision. On a 2-layer board, your "return path" is whatever copper the current can find, and above a few MHz that assumption falls apart. Four layers give you dedicated planes. Six layers give you enough planes to stop making compromises. This article walks through how each stackup assigns its copper, what that does to signal integrity and power delivery, and the concrete signal-count and edge-rate thresholds where adding layers stops being optional.
The default 4-layer stackup and why it works
The canonical 4-layer arrangement is Signal – Ground – Power – Signal. The outer layers carry traces, and the two inner layers are solid copper pours: a continuous ground plane directly under the top signal layer and a power plane above the bottom signal layer. This single decision buys you most of the benefit of going multilayer.
Why it matters: a high-speed signal's return current does not flow back through the nearest ground pin. It flows in the reference plane directly beneath the trace, mirroring the signal path to minimize loop inductance. A solid plane one dielectric away means that return path is continuous and tightly coupled. With a typical prepreg of 0.1–0.2 mm between the top signal and the ground plane, you can hit a repeatable 50 Ω single-ended or 90–100 Ω differential microstrip with trace widths your fab can actually hold.
Rule of thumb: keep every high-speed trace referenced to a solid, unbroken plane. On 4 layers that is easy for the top signal layer and risky for the bottom, which references a power plane that may be split across rails.
Where 4 layers starts to hurt
The weakness of S-G-P-S is the bottom signal layer. It references the power plane, and power planes are rarely one clean rail. The moment you split that plane into 3.3 V, 1.8 V, and 1.2 V islands, any trace crossing a split loses its return path. The return current has to detour around the gap, enlarging the loop, radiating EMI, and injecting crosstalk. You can patch this with stitching capacitors near the crossing, but you are now designing around a limitation instead of routing freely.
The second problem is density. With only two routing layers, a dense BGA with 0.8 mm pitch and 200+ signals forces you into tight, meandering routes and via-in-pad tricks. You run out of channels before you run out of nets.
The 6-layer answer: two planes to spare
A common high-performance 6-layer stackup is Signal – Ground – Signal – Power – Ground – Signal. Now the two inner signal layers are each adjacent to a full reference plane and are buried as stripline — shielded above and below — which cuts radiated emissions dramatically. The outer layers stay available for easy-to-rework components and less-critical routing, and crucially you get a ground–power–ground core.
That GND/PWR/GND core creates a tightly-coupled plane-pair capacitor. The inter-plane capacitance (tens of pF per cm² at ~3–4 mil separation) supplies charge at frequencies where discrete decoupling capacitors are already inductive — typically above a few hundred MHz. This is the single biggest power-delivery-network advantage of six layers, and it is why you sign-off a PDN with a tool like Cadence Sigrity or Siemens HyperLynx PI rather than guessing.
Signal integrity and cost, side by side
| Factor | 4-Layer (S-G-P-S) | 6-Layer (S-G-S-P-G-S) |
|---|---|---|
| Routing layers | 2 | 4 |
| Reference planes | 1 GND + 1 split PWR | 2 GND + 1 PWR |
| Inner signals shielded (stripline) | No (both signal layers external) | Yes (2 layers) |
| Return path over split planes | Risk on bottom layer | Every layer sees a full plane |
| Plane-pair PDN capacitance | Weak (G/P far apart) | Strong G-P-G core |
| Relative bare-board cost | Baseline (1.0×) | ~1.2–1.4× |
Cost reality: fab cost does not double when you double the planes. Panel setup, drilling, and electrical test dominate small-run pricing, so a 6-layer board is often only 20–40% more than 4-layer at prototype quantities — frequently cheaper than the engineering time spent fighting a cramped 4-layer design.
Concrete thresholds: when to add the layers
- Edge rate, not clock rate. A 20 MHz clock with a 500 ps rise time has significant energy past 700 MHz (f ≈ 0.35 / tr). Fast edges — DDR3/DDR4, USB 3.x, PCIe, gigabit Ethernet, MIPI — are the trigger, and they almost always want six layers for clean referencing.
- Net count vs. BGA pitch. If a 0.8 mm-pitch BGA breaks out more signals than two layers can escape, you need inner routing. As a guide, past ~150–200 routed nets on a dense part, go to six.
- Split power rails under fast traces. If routing forces high-speed nets across a split power plane on a 4-layer board, that is the clearest signal to add a second ground plane.
- EMC margin. If you expect to fight radiated-emissions compliance, burying your clocks as stripline on six layers often saves a re-spin.
For the mechanics of symmetric construction, copper-balance to avoid warpage, and dielectric selection, see our companion piece on PCB stackup design fundamentals, and the deeper treatment of return paths in reference planes and return-current control. If you are evaluating a design for manufacturability or SI sign-off, Avecas design services runs the kind of pre-layout and post-route checks these tradeoffs demand.
Want to go from "which stackup?" to confident impedance-controlled routing with real SI/PI sign-off? The CourseTron PCB & High-Speed Design track walks you through stackup planning, HyperLynx/Sigrity analysis, and DDR layout on real boards.
FAQ
Can I just use a thicker 4-layer board instead of 6 layers?
Thickness does not add reference planes. A thicker 4-layer board worsens impedance control because the dielectric to your reference plane grows, forcing wider traces. If your problem is referencing or routing density, only more layers solve it.
Why not 6 layers with four signal layers and only two planes?
You can, but a stackup like S-S-G-P-S-S leaves signal layers referencing each other instead of a plane, which recreates the crosstalk and return-path problems you paid to escape. Keep every signal layer adjacent to a solid plane; that is the whole point of going to six.
Is 4-layer ever better than 6 for high speed?
For low pin-count parts with slow edges — most MCU, motor-control, and sensor boards — a clean 4-layer S-G-P-S is lighter, cheaper, and perfectly adequate. Adding layers you do not need adds cost and lead time with no SI benefit.
Does the 6-layer plane capacitance replace decoupling capacitors?
No — it complements them. Discrete capacitors handle low and mid frequencies; the tightly-coupled plane pair covers the high-frequency band where those capacitors have gone inductive. A PDN tool models both so you place the right values, not a scattershot of 0.1 µF parts.