In short: Length matching equalizes the propagation delay of related signals by adjusting copper trace length (often with serpentine wiggles) so that edges arrive within a tolerable skew budget — a few picoseconds for SerDes lanes, tens of picoseconds for DDR byte lanes.
On a fast PCB a signal is not an abstraction that appears everywhere at once. It is a wave of energy crawling down a copper trace at a finite speed. When two signals must be sampled together — the 8 bits of a DDR byte lane, the true and complement of a differential pair, the lanes of a PCIe link — any difference in their arrival time steals from your timing margin. Length (really *delay*) matching is the discipline of keeping that difference inside a budget you can defend.
Why delay, not length, is what you really match
A signal propagates at v = c / √εr_eff. On FR-4 a stripline sees an effective dielectric constant near 4.2, giving roughly 180 ps per inch (about 7 ps/mm); a microstrip, with part of its field in air, is faster at ~150 ps/inch. The headline number designers quote — "match to within 5 mil" — is a proxy for a time number. Convert first: 5 mil on that stripline is only about 0.9 ps of skew. The reason we match *length* is that on a uniform layer, length is the knob we control; the moment two traces run on layers with different εr_eff, equal length no longer means equal delay, and you must match delay explicitly. Tools such as Cadence Allegro, Siemens Xpedition and Altium let you define matched-length groups with a per-layer velocity so the constraint engine compares picoseconds, not millimetres.
Rule of thumb: ~150 ps/inch on microstrip, ~180 ps/inch on FR-4 stripline. Always translate a length tolerance into a time tolerance before you trust it.
Building a skew budget from the timing diagram
A skew budget is not a number you inherit — you derive it. Start from the receiver's setup/hold window and the unit interval (UI), then subtract every contributor: driver output skew, clock jitter, package delay mismatch, ISI, crosstalk-induced jitter, and the via/connector transitions. Whatever is left is yours to spend on routing. For a DDR4 data group at 1600 MT/s the UI is 625 ps; a typical routing skew allowance inside a byte lane is about 5 ps (roughly 25 mil), tight because the write/read data strobe (DQS) must stay centred in the data eye.
| Interface | Data rate | Typical intra-group skew target | ≈ length tolerance (stripline) |
|---|---|---|---|
| DDR4 byte lane | 1600–3200 MT/s | ~5 ps | ~25 mil |
| DDR4 address/command to CK | fly-by | ~10 ps | ~50 mil |
| PCIe Gen4 lane (within pair) | 16 GT/s | ~1 ps (intra-pair) | ~5 mil |
| USB 3.2 / SerDes intra-pair | 5–10 Gbps | <1 ps | ~3–5 mil |
Serpentine routing — the tool and its traps
When one trace is short, you lengthen it with a serpentine (accordion) section. It works, but it is not free. Each tight bend couples the trace to itself: the inner edges of adjacent segments see a shorter path, so a serpentine actually propagates slightly *faster* than a straight trace of the same copper length — the so-called serpentine speed-up. Keep the gap between parallel segments at least 3× to 4× the trace width (3W–4W) to limit self-coupling, and prefer rounded or 45° corners over sharp 90° turns.
Watching the edge travel — delay in motion
The animation below makes the point physical: an unmatched pair samples at different instants, so the receiver latches stale data. Matching the delay lines the edges up at the sampling clock.
DDR fly-by: match to the clock, then de-skew
DDR3/4/5 abandoned the old "tree" topology for address/command/control in favour of fly-by: the clock and command bus snake past each DRAM in series, one chip after another. This gives clean signal integrity but deliberately introduces a staggered arrival — the last DRAM sees CK later than the first. The data groups are therefore not matched to the command bus; instead each DQ/DQS byte lane is matched tightly within itself, and the controller's write leveling trains per-byte delays to absorb the fly-by skew. The routing job is: match intra-byte-lane hard, match DQS-to-DQ even harder (it is the sampling reference), and let the silicon handle the rest.
In a fly-by DDR layout you intentionally do not length-match data to address/command. You match within each byte lane and rely on write leveling for the rest.
SerDes and differential pairs: intra-pair is king
For multi-gigabit SerDes (PCIe, USB, SATA, Ethernet) the hierarchy flips. Inter-lane skew is forgiving because each lane has its own clock-data recovery (CDR), but intra-pair skew — the mismatch between P and N of a single differential pair — is brutal. Any P/N length difference converts common-mode, degrades the eye and radiates EMI. Target sub-picosecond intra-pair skew, and correct it right at the source of the mismatch (usually a bend or a pin-escape) with a small bump, not with a serpentine far down the trace. This connects directly to good differential pair routing, where symmetric geometry is the first line of defence. For layer-transition delay — a frequent hidden offender — see our note on via stubs and layer transitions.
A practical matching checklist
- Convert every length tolerance to picoseconds using the correct per-layer velocity.
- Fix intra-pair skew at its origin; never cancel it with a distant wiggle.
- Use 3W–4W serpentine spacing and 45°/rounded corners.
- Account for via and connector delay — a thru-via can add several ps.
- Let the constraint manager (Allegro/Xpedition/Altium) enforce matched groups by delay, and verify with a field solver for critical nets.
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Frequently Asked Questions
Is it length or delay that actually needs to match?
Delay. Length matching is a convenient proxy that only holds when two traces share the same layer and dielectric. Cross layers and you must match propagation delay directly, because εr_eff — and therefore velocity — changes.
Why does a serpentine propagate slightly faster than a straight trace?
Adjacent segments couple to each other, and the inner edges of the bends present a shorter electrical path. The signal "shortcuts" across the folds, so the effective delay is a little less than the physical copper length implies — budget a small margin for it.
Do I length-match DDR data to the address/command bus?
No. Modern DDR uses a fly-by topology that intentionally staggers clock and command arrival. You match within each byte lane (and DQS to DQ) and let the controller's write-leveling training compensate for the fly-by skew.
How tight must intra-pair skew be for PCIe Gen4?
Around 1 ps or roughly 5 mil of stripline, and ideally corrected at the point of mismatch. Intra-pair skew turns differential energy into common-mode, closing the eye and raising EMI far more than inter-lane skew does.