In short: An impedance discontinuity is any point where a trace's instantaneous impedance deviates from its target (usually 50 Ω single-ended or 100 Ω differential) — a stub, a via, or a connector launch — and each one reflects part of the signal back toward the source, degrading eye margin; you find them with a TDR and fix them by tapering, back-drilling, and tuning the launch.
Controlled impedance is only half the battle. You can route a perfect 50 Ω microstrip and still fail compliance because the signal never travels along uniform copper for long — it passes through a connector, dives through a via to an inner layer, and often drags an unused stub behind it. Each of those transitions is a place where the characteristic impedance changes abruptly, and a changing impedance is exactly what a high-speed edge cannot tolerate.
Why a discontinuity reflects
When a fast edge meets a boundary between impedance Z1 and Z2, part of the energy transmits and part reflects. The reflection coefficient is
Γ = (Z2 − Z1) / (Z2 + Z1)
A 50 Ω line hitting a 75 Ω section gives Γ = 25/125 = 0.20 — 20% of the voltage bounces straight back. That reflected wave races to the driver, re-reflects off the driver's own impedance, and returns as inter-symbol interference that closes the eye. The higher the data rate, the shorter the rise time, and the more spectral energy sits at frequencies where even a small physical feature looks electrically long.
Rule of thumb: a feature behaves as a discontinuity once its electrical length exceeds roughly 1/10 of the signal's rise time. At a 40 ps edge (PCIe 5.0 territory), that is about 2 mm of propagation — so a 1.6 mm via stub is already a real antenna.
The three usual suspects
- Stubs. A stub is a dead-end branch — most commonly the unused portion of a through-via below the layer where the signal actually exits. The stub resonates at a quarter-wavelength, creating a sharp suck-out notch in the insertion loss. A 1.5 mm stub in FR-4 notches near ~15 GHz, right inside a 32 GT/s channel.
- Vias. Even a perfectly short via is a capacitive/inductive lump: the antipad, barrel, and pads form a small LC network whose impedance dips well below 50 Ω. Stacked and staggered microvias behave differently again.
- Connectors. The launch from a board pad into a connector pin is where geometry changes most violently — ground reference shifts, pin inductance appears, and the solder fillet adds capacitance. SMA, SMP, and high-speed card-edge launches are all notorious.
Seeing them with TDR
Time-Domain Reflectometry is the microscope for this problem. A TDR launches a fast step into the line and watches the reflected voltage versus time. Because time maps to distance (about 150 ps per inch in FR-4, round trip), the plotted impedance profile is effectively a map of your channel: an upward bump means a locally high impedance (series inductance, a gap in the reference plane), a downward dip means low impedance (a pad, a via, excess capacitance). Modern sampling scopes — Keysight, Tektronix — and the TDR mode in field solvers let you correlate each wiggle to a physical feature. In simulation, Cadence Sigrity, Siemens HyperLynx, and Synopsys/Ansys 3D field solvers produce the same profile from the layout before the board is even fabricated, which is where the real savings are.
| Discontinuity | TDR signature | Typical fix |
|---|---|---|
| Via stub | Dip + resonant notch in S21 | Back-drill / blind-buried via |
| Via transition | Short downward dip (capacitive) | Enlarge antipad, tune pad size |
| Connector launch | Sharp spike or dip at the edge | Taper trace, ground-via fence |
| Reference-plane gap | Upward bump (inductive) | Add stitching cap / continuous plane |
Fixing each one
Stubs: back-drilling (controlled-depth drilling that removes the unused barrel) is the standard cure for long through-vias on thick backplanes, leaving a residual stub of 0.2–0.3 mm. Where cost allows, blind and buried vias eliminate the stub entirely. Vias: treat them as a tunable structure — widen the antipad to cut capacitance, keep the return path continuous with ground vias beside the signal via, and avoid oversized pads. Connectors: follow the vendor's launch footprint exactly, use a smooth trace taper into the pin, and surround the launch with a ground-via fence so the return current has somewhere to go. The guiding principle in every case is to restore impedance continuity, the same discipline covered in our deep dive on controlled-impedance PCB design and in the related guide to return-path and reference-plane design.
Back-drill payoff: trimming a 1.8 mm stub to 0.25 mm on a 28 Gbps backplane can recover several dB of insertion loss at the Nyquist frequency and move the resonant null well above the band of interest — frequently the difference between a passing and failing eye.
For teams moving from theory to signed-off stackups, structured SI training like the courses at ChipXpert's VLSI and hardware programs pairs well with hands-on field-solver practice.
Want to measure, simulate, and fix real discontinuities with Sigrity and HyperLynx? Our CourseTron Signal Integrity & High-Speed PCB course walks you from TDR capture to a back-drilled, compliant channel.
Frequently asked questions
Is every via a problem?
No. At low speeds a via is electrically invisible. It only matters once its electrical length approaches a tenth of the edge rise time; below a few hundred Mbps you can usually ignore via parasitics entirely.
TDR or frequency-domain S-parameters — which should I trust?
They are two views of the same data. TDR localizes a defect in space ("the problem is at the connector"), while S-parameters quantify its effect across frequency. Use TDR to find and fix, use insertion/return loss to prove compliance.
Does back-drilling always help?
Only when the stub is the dominant loss mechanism. On thin boards with short vias the stub may already be negligible, and back-drilling adds cost and a small residual. Simulate first.
Can I fix a bad connector launch in layout alone?
Often yes — tapering the trace, matching the vendor footprint, and fencing with ground vias usually recovers most of the margin. If the connector itself is the limit, you change the part, not the board.