Full Adder using Half Adders

In short: A full adder is two half adders chained (the first adds A and B, the second adds that partial sum to the carry-in) with an OR gate merging the two carry outputs, giving Sum = A ⊕ B ⊕ Cin and Cout = AB + Cin(A ⊕ B).

Why build a full adder from half adders at all?

A half adder adds two single bits and produces a sum and a carry. It has no input for a carry arriving from a lower bit position, so it can only ever serve as the least significant stage of a multi-bit adder. To add 4-bit, 32-bit or 64-bit numbers you need a cell that accepts three inputs: A, B and a carry-in (Cin). That cell is the full adder.

Interviewers love this topic because it tests whether you can derive hardware from a truth table rather than memorise a diagram. The half-adder decomposition is the cleanest derivation, and it sets up the discussion of gate count and delay that leads into the ripple-carry adder.

Half adder recap

For inputs A and B, the half adder implements two functions:

• Sum = A ⊕ B (XOR): 1 when exactly one input is 1.
• Carry = A · B (AND): 1 only when both inputs are 1.

Adding 1 + 1 gives binary 10, so the sum bit is 0 and the carry is 1. That single row is the reason the carry output exists, and it will matter again when we justify the OR gate.

The construction, step by step

Treat the three-input addition as two sequential two-input additions:

• Stage 1: HA1 adds A and B, producing a partial sum S1 = A ⊕ B and a partial carry C1 = A·B.
• Stage 2: HA2 adds S1 and Cin, producing the final Sum = S1 ⊕ Cin and a second carry C2 = S1·Cin.
• Merge: Cout = C1 + C2, implemented with a single OR gate.

Deriving the equations

Substituting stage by stage:

• Sum = S1 ⊕ Cin = A ⊕ B ⊕ Cin. XOR is associative, so the grouping does not change the answer; it only decides the physical structure.
• Cout = C1 + C2 = AB + Cin(A ⊕ B).

Key fact: the sum output is simply the parity of the three inputs. It is 1 whenever an odd number of A, B and Cin are 1.

You can verify Cout against the sum-of-products form from a Karnaugh map: Cout = AB + BCin + ACin, the majority function. Expanding Cin(A ⊕ B) = Cin·A·B' + Cin·A'·B and adding AB, then absorbing terms, yields the same majority expression. Cout is 1 whenever at least two of three inputs are 1.

Truth table with internal nodes

Look at the last row: 1 + 1 + 1 = 3, which is binary 11, so Sum = 1 and Cout = 1. HA1 produces C1 = 1 (from 1 + 1) and S1 = 0. HA2 then adds 0 + 1, giving Sum = 1 and C2 = 0. The carry comes entirely from HA1.

Why an OR gate and not an XOR?

This is the classic follow-up question. The two carries can never be 1 at the same time. C1 = 1 requires A = B = 1, which forces S1 = 0. But C2 = S1·Cin needs S1 = 1. The two events are mutually exclusive, so OR, XOR and even a wired combination are logically equivalent here. Designers choose OR because it is cheaper than XOR in standard cells: a 2-input OR is typically a fraction of the area of an XOR2 in most libraries.

Key fact: C1 and C2 are mutually exclusive in every one of the eight input rows, which is why the carry merge can be a plain OR.

Watching the bits flow

The animation below sends the input combination 1, 1, 1 through the structure. Notice the highlighted pulse leaving HA1 on the carry path while the sum path carries a 0 into HA2.

Gate count, delay and what synthesis does

The half-adder build uses 2 XOR, 2 AND and 1 OR: five gates. The critical path from A or B to Cout goes through HA1's XOR, HA2's AND, then the OR: roughly XOR + AND + OR delays. From Cin, the path is shorter: just AND then OR, which is why ripple chains are optimised around the carry path.

In a real flow you would almost never rely on this exact structure surviving. If you write assign {cout, sum} = a + b + cin; in RTL, Synopsys Design Compiler or Cadence Genus will usually map it to a dedicated full-adder cell (such as an FA cell in the foundry library), since a single compound cell has less internal routing and lower delay than five discrete gates. Understanding the decomposition still matters for debugging, for ECOs, and for custom or full-custom design where you do pick transistors. A typical static CMOS mirror adder needs about 28 transistors; a transmission-gate version can be smaller.

module full_adder(input a, b, cin, output sum, cout);
  wire s1, c1, c2;
  half_adder ha1(.a(a),  .b(b),   .s(s1),  .c(c1));
  half_adder ha2(.a(s1), .b(cin), .s(sum), .c(c2));
  assign cout = c1 | c2;
endmodule

Key fact: simulators such as Siemens Questa or Synopsys VCS will confirm this structural model matches the behavioural a + b + cin in an exhaustive 8-vector test, which is a standard first testbench exercise.

If you want to practise this hands-on with real EDA flows, the training team at ChipXpert runs instructor-led VLSI batches, and our structured modules live on the CourseTron courses page. A natural next topic is the carry-lookahead idea in carry-lookahead adders, which removes the serial carry dependency.

Ready to go beyond adders? Join the CourseTron Digital Electronics course and build, simulate and synthesise arithmetic blocks yourself.

Frequently asked questions

Why can't a half adder be used for every bit position?

It has no carry-in input, so it cannot accept the carry generated by the lower bit. Only the least significant bit, which has no incoming carry, can use one.

Can I use an XOR instead of the OR gate for Cout?

Yes, functionally. C1 and C2 are never both 1, so XOR and OR give identical results. OR is chosen because it is smaller and faster in most cell libraries.

How many gates does a full adder need from half adders?

Five: two XORs, two ANDs and one OR. Libraries often provide a single optimised FA cell instead.

What is the logic equation of the full adder carry?

Cout = AB + Cin(A ⊕ B), which simplifies to the majority function AB + BCin + ACin.