In short: A half adder adds two single bits using one XOR gate for the sum (S = A ⊕ B) and one AND gate for the carry (C = A·B), but it has no input for an incoming carry, so it can only start a chain of additions and never continue one.
What a half adder actually does
Binary addition of two one-bit numbers has only four cases: 0+0=0, 0+1=1, 1+0=1 and 1+1=10 (binary for two). The result needs two output bits, so the circuit has two outputs: Sum, the bit that stays in the current column, and Carry, the bit that spills into the next column. The "half" in the name means the circuit handles only half of the job of a complete adder cell. It adds the two operand bits of a column but ignores whatever the column to the right may have pushed in.
This is the smallest arithmetic circuit you can build, and it shows up in nearly every digital design interview because the whole story of a processor's ALU grows out of it.
The truth table
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Read the Sum column on its own: it is 1 exactly when the inputs differ. That is the definition of XOR. Read the Carry column: it is 1 only when both inputs are 1, which is AND. Nothing more is needed, so the circuit costs two gates.
Key fact: Sum is the parity of the inputs and Carry is their logical AND. Both ideas generalise directly to the full adder.
K-map derivation
A Karnaugh map confirms the result systematically. Put A on the rows and B on the columns, and fill one map for each output.
On the Sum map the two 1s sit diagonally. Cells that touch only at corners are not logically adjacent, so the K-map cannot merge them, and the minimal sum-of-products is A'B + AB'. That expression is precisely XOR. The Carry map has one lone 1 at A=1, B=1, giving C = AB. Whenever a K-map shows a checkerboard pattern, you are looking at an XOR (or XNOR) function, a useful reflex for interviews.
The gate-level circuit
Because the two gates work side by side, the critical path is a single gate delay, either XOR or AND, whichever is slower. XOR is normally the slower one: in static CMOS a standard XOR2 cell uses about 10 to 12 transistors against 6 for AND2, and its delay is typically 1.5 to 2 times that of a simple gate.
Watch it compute
Why it cannot accept a carry-in
Look at the schematic again: there are exactly two input pins. Add two 4-bit numbers, 0110 (6) plus 0111 (7). Bit 0 is 0+1, fine. Bit 1 is 1+1, giving sum 0 and carry 1. Bit 2 must now add three bits: A2=1, B2=1 and the carry from bit 1. A half adder has no third pin, so the carry produced one column earlier has nowhere to go. If you wire only A2 and B2, the carry is dropped and the result is wrong: the correct answer is 1101 (13), but the dropped carry makes bit 2 come out as 0 instead of 1.
The fix is a cell with three inputs, A, B and Cin, that produces Sum = A ⊕ B ⊕ Cin and Cout = AB + Cin(A ⊕ B). That cell is the full adder, and it is classically built from two half adders plus an OR gate: the first half adder adds A and B, the second adds its sum to Cin, and OR merges the two possible carries (they can never both be 1).
Key fact: Two half adders and one OR gate make a full adder. That is why the half adder is called a building block rather than a standalone adder.
So where is a half adder used by itself? In the least significant bit of an adder, where no carry-in exists, in incrementers (adding a constant 1 reduces each column to a half adder), and in the partial-product reduction trees of multipliers. Our ripple-carry adder article shows how chains of these cells stack up delay.
Implementation notes and interview traps
- RTL: write it as
assign {c, s} = a + b;and let synthesis choose cells, or writes = a ^ b; c = a & b;explicitly. Synopsys Design Compiler and Cadence Genus both map this onto library XOR2/AND2 cells, or onto a dedicated half-adder cell (often named HA or HADD) if the standard-cell library provides one. - NAND-only form: the half adder needs five NAND2 gates: four form the XOR, and the first NAND's output, inverted by a fifth NAND, gives the carry. Interviewers like asking for this.
- Verification: with two inputs, simulation in Siemens Questa or Synopsys VCS can cover all four vectors exhaustively, so there is no excuse for partial coverage.
- Common trap: claiming OR gives the sum. OR gives 1 for 1+1, which is wrong; the sum of 1+1 is 0 with a carry.
If you want to see how these small cells are sized, placed and timed in a real chip flow, the team at Avecas design services works on exactly this level of standard-cell and datapath implementation.
Ready to go from single gates to full datapaths? Explore the digital electronics tracks on CourseTron courses and practise adders, ALUs and timing with guided labs.
Frequently asked questions
Why is a half adder called "half"?
It adds only the two operand bits and cannot take a carry from a lower column, so it implements half of what a full adder does.
What are the Boolean expressions of a half adder?
Sum = A ⊕ B = A'B + AB', and Carry = A·B.
How many half adders make a full adder?
Two half adders plus one OR gate. The OR combines the carry from each half adder into Cout.
Can I build a multi-bit adder from half adders only?
Only the lowest bit can use a half adder. Every higher bit needs a carry-in, so it needs a full adder.
References & Further Reading
Related training: ChipXpert VLSI training.