SISO Shift Register

In short: A serial-in serial-out (SISO) shift register is a chain of N D flip-flops that delays a bit stream by exactly N clock cycles, so it works as a cheap, programmable-by-length digital delay line.

Why a shift register is really a delay line

Most textbooks introduce the SISO register as a storage curiosity. In real silicon it earns its keep as a delay element. Each D flip-flop samples its input on a clock edge and holds it for one full period. Chain N of them, tie every clock pin together, and a bit that enters the first stage reappears at the last stage N edges later. Nothing about the data is changed; only its position in time moves. That is a pure latency of N cycles.

This matters whenever two signals must line up. A control flag that is produced early has to wait while its data finishes a multi-cycle multiplier. An input that arrives from a sensor needs to be aligned with a pipeline stage. A serial protocol decoder needs the bit seen three cycles ago. In all of these, a short SISO chain is the smallest correct answer, and it is also the pattern you will be asked to draw in an interview. If you want the parallel-load sibling, read our guide to the PIPO shift register afterwards.

The structure: N flip-flops, one data path

The wiring is deliberately boring. Din goes to the D pin of FF1. Q1 goes to D2, Q2 to D3, Q3 to D4, and the serial output is Q4. There is no mux, no enable and no logic between stages, which is exactly why it is so fast. The only design variables are the number of stages N and the clock frequency f. The delay in time is simply N divided by f.

Key fact: Latency in cycles equals the number of flip-flops, N. Latency in time equals N / f_clk. A 4-stage register at 100 MHz delays by 40 ns; an 8-stage one by 80 ns.

Reading the timing diagram

Take a 4-bit register that starts cleared (0000) and feed it the serial pattern 1, 0, 1, 1, followed by zeros. The state after each rising edge is the best way to see the behaviour.

Read Q4 from edge 4 to edge 7: 1, 0, 1, 1. That is the input stream, intact, four cycles late. Notice also the dead time. For the first three edges the output is whatever the register was reset to. In a real design this startup window is why delay chains are often paired with a valid bit or a short warm-up counter; otherwise downstream logic consumes garbage from the pre-fill period.

See it move

The animation makes one subtle point visible. Every flip-flop updates at the same instant, so a bit never races through two stages in one cycle. That guarantee comes from edge triggering and from the clock-to-Q delay being longer than the hold requirement of the next flop, which brings us to timing closure.

Timing: what actually limits the clock

With no logic between stages, the path from one flop to the next consists only of clock-to-Q (t_cq) plus the setup time (t_su) of the receiver. Suppose a library has t_cq of 0.35 ns and t_su of 0.10 ns, and the clock skew budget is 0.05 ns. The minimum period is about 0.50 ns, so the register core alone could run near 2 GHz. In practice the clock tree, I/O or the logic around it cap you long before that, which is a good reason never to blame the shift chain for a setup failure.

The real danger is hold. Because t_cq of one flop feeds the next flop directly, the margin is t_cq(min) minus hold time minus skew. If the clock reaches FF2 0.3 ns later than FF1 and t_cq(min) is only 0.25 ns, the new value of Q1 arrives at D2 before FF2 has finished capturing the old one, and the bit skips a stage. Static timing tools such as Synopsys PrimeTime or Cadence Tempus report this as a hold violation, and the fix is to insert delay buffers or a lock-up latch on the offending hop. Scan chains in DFT are nothing more than long SISO registers, so this exact failure is the most common reason a scan shift test fails on silicon.

Key fact: A shift chain has almost no setup problem and a large hold problem. Skew between neighbouring flops, not logic depth, is what breaks it.

Implementation choices: flops, SRLs and RAM

When N is small, plain flip-flops are right. For long delays, say 64 or 1,000 cycles, burning a thousand flops wastes area and power, because every flop toggles with the clock. FPGA vendors know this. Xilinx and AMD devices can pack a shift register of up to 32 bits into a single LUT configured as an SRL, and Intel offers the altshift_taps megafunction that maps to block RAM. In ASIC flows the equivalent trick is a small dual-port RAM with a circular read-write pointer, trading the shift for an address counter. The cost is a read latency you must count carefully, since a synchronous memory adds one more cycle.

• Flip-flop chain: best below roughly 8 to 16 stages, zero control logic, easiest timing.
• LUT-based SRL: dense, but no reset on the data bits and one extra clock-to-out delay.
• RAM with pointers: best for hundreds of cycles, needs an address counter and careful latency accounting.

Synthesis tools usually infer the right structure from a three-line RTL description, but you should always confirm in the utilization report. A chain that you expected to become an SRL may be kept as flops if you added an asynchronous reset to every stage.

Common mistakes and interview traps

• Off-by-one latency: counting the input flop as zero delay. With N flops the output lags by N edges, not N minus 1. If you also register the output, you add another cycle.
• Blocking assignments in RTL: writing q1 = d; q2 = q1 inside a clocked block collapses the chain into one flop in simulation. Use non-blocking assignments (<=).
• Ignoring reset values: unreset chains show X on the output for N cycles in simulation, and that propagates into scoreboards.
• Treating it as a clock divider or counter: a plain SISO chain does not change frequency; it only shifts time.

always @(posedge clk) begin
  q <= {q[2:0], din};   // 4-stage SISO
end
assign dout = q[3];       // delayed by 4 cycles

If you need to load all stages at once and still read serially, that is the parallel-in variant, and it uses a mux in front of every flop. We cover it, plus the area cost of those muxes, in the universal shift register guide. For engineers who want to see delay chains handled on a real tape-out, the physical-design team at Avecas design services works through hold-fixing on scan chains daily.

FAQ

How many clock cycles does a SISO shift register delay a signal?

Exactly as many cycles as it has flip-flops. A 6-bit SISO register delays its input by 6 clock periods, which is 6 divided by the clock frequency in seconds.

Why is the first valid output not available immediately?

The register must fill. Until N edges have passed, the output reflects the initial or reset contents rather than your data, so designs add a valid flag or discard the first N samples.

What is the maximum clock frequency of a shift register?

It is bounded by 1 / (t_cq + t_su + skew) for a single hop. For typical libraries that is in the gigahertz range, but hold violations from clock skew are usually the real constraint.

Can a SISO shift register replace a FIFO?

Only for fixed latency with a steady stream. A FIFO tolerates variable arrival and read rates; a shift register always advances on every enabled clock and cannot absorb bursts.

Want to build, simulate and close timing on circuits like this yourself? Explore the hands-on digital design tracks in our CourseTron courses, or sharpen your lab skills with instructor-led batches at ChipXpert VLSI training.