SIPO Shift Register

In short: A SIPO (serial-in, parallel-out) shift register is a chain of D flip-flops that captures one serial bit per clock edge and, after N clocks, presents all N bits at once on N output pins, which is how a microcontroller with three pins can drive dozens of outputs.

What a SIPO shift register actually does

A serial link carries one bit per clock cycle on a single wire. Most loads, such as LEDs, relay drivers, DAC input words and bus registers, want all their bits at the same instant. The SIPO register is the bridge between those two worlds. It is built from N edge-triggered D flip-flops wired in a line: the data input of flip-flop 0 is the external serial pin, and the D input of every other flip-flop is the Q output of its left neighbour. All clock pins are tied together.

On every active clock edge, every flip-flop samples its D input simultaneously. Because each D input is the old Q of the previous stage, the stored word moves one position and one new bit enters at the end. After N edges, the first bit you sent has travelled to the far end, and the register holds the complete N-bit word. Reading the outputs Q0 to Q(N-1) in parallel gives you the converted data.

Truth table: tracing the stream 1, 0, 1, 1

Assume the register is cleared to 0000 and the sender transmits MSB first: 1, 0, 1, 1. The next-state equations are Q0(next) = Din and Qn(next) = Q(n-1) for n = 1 to 3. Writing the state as Q3 Q2 Q1 Q0:

After the fourth edge the parallel word reads 1011, exactly the order in which the bits were sent. Note the direction convention: when data enters at Q0 and moves toward Q3, the first bit sent ends up at Q3. If your sender is LSB first, the final parallel word is bit-reversed, a classic source of bugs in bring-up.

Key fact: N bits need N clock edges, but the parallel word is only valid after the Nth edge. Anything that samples the outputs earlier sees a half-shifted, garbage word.

Watching the bits move

The animation below pushes a 1 into the register and shifts it through all four stages, one position per clock tick.

Where SIPO registers are used in real designs

• Output expansion: The 74HC595 is an 8-bit SIPO with a storage latch. Three GPIO pins (data, shift clock, latch clock) can drive 8 LEDs, and chaining 4 devices gives 32 outputs with the same 3 pins.
• Serial deserialisers: SerDes receivers, UART receive paths and SPI slaves shift incoming bits into a shift register, then transfer the completed byte into a holding register.
• Scan chains: In DFT, every scan flop acts as a stage of a giant shift register. Tools such as Synopsys DFT Compiler, Cadence Modus and Siemens Tessent stitch thousands of flops into chains, shift a pattern in, pulse a capture clock and shift the response out.
• Protocol framing: Pattern detectors for sync words (for example a start-of-frame marker) look at the parallel outputs of a SIPO and compare them to a constant every cycle.

The sibling operation is covered in our guide to the PISO shift register, which does the reverse job of turning a parallel word into a serial stream. Together they form the two ends of a serial link, and you can see how both fit into the wider family in our article on universal shift registers.

Timing and design pitfalls interviewers love

The ideal picture hides three practical issues.

• Hold-time violation: Stage n+1 samples Q of stage n at the same edge that stage n is updating. Clock-to-Q delay normally exceeds the hold requirement, so it works. But with clock skew where the downstream flop receives a late clock, the new value races through and the bit is shifted twice. Static timing tools such as Synopsys PrimeTime and Cadence Tempus report this as a hold violation, and the fix is delay buffers on the data path, not a slower clock.
• Intermediate outputs: The parallel outputs change on every clock, so a downstream circuit sees partial words. That is why the 74HC595 adds a latch: the output register updates only on a separate latch pulse once the shift is complete.
• Asynchronous serial input: If Din comes from another clock domain, the first flop can go metastable. Use a two-flop synchroniser before the shift chain.

Key fact: Maximum shift frequency is limited by clock-to-Q plus setup, but since there is no logic between stages, SIPO chains are usually the fastest structures in a design. Hold fixing, not setup, is the typical problem.

Writing it in Verilog

module sipo #(parameter N = 8) (
  input  wire         clk,
  input  wire         rst_n,
  input  wire         din,
  output reg  [N-1:0] q
);
  always @(posedge clk or negedge rst_n)
    if (!rst_n) q <= {N{1'b0}};
    else        q <= {q[N-2:0], din};
endmodule

The concatenation shifts left, placing the new bit in position 0, so the first bit sent ends in q[N-1]. Always use non-blocking assignments here: a blocking assignment would let the new value ripple through every stage in zero time and collapse the register into a single flop. Synthesis tools such as Synopsys Design Compiler and Cadence Genus map this directly to N scan-capable flops with no combinational logic.

Practical sizing example

Suppose you must drive a 16-bit DAC from an MCU that only has an SPI port clocked at 10 MHz. Sending a 16-bit word takes 16 clocks, or 1.6 microseconds. A 16-bit SIPO captures the word and a latch presents it to the DAC in one cycle, giving a maximum update rate of roughly 625 kHz. If that is too slow, the answer is a faster serial clock or a wider parallel bus, which is exactly the serial-versus-parallel trade-off interviewers want you to discuss.

If you want hands-on practice taking designs like this through synthesis, STA and DFT insertion, explore the CourseTron courses. For industry-style lab training, ChipXpert's VLSI training programmes cover the full flow.

Ready to master sequential design? Join the Digital Electronics track on CourseTron and build, simulate and time shift registers yourself.

FAQ

What is the difference between SIPO and PISO?

SIPO takes serial data in and delivers it in parallel after N clocks. PISO loads a parallel word at once and shifts it out serially, one bit per clock.

How many clock pulses does a SIPO need?

An N-bit SIPO needs N clock pulses to load a full word, so a 8-bit register needs 8 pulses before its outputs hold the complete byte.

Why does the 74HC595 have a separate latch?

The latch holds the outputs steady while new data shifts in, so loads never see half-shifted words.

Can a SIPO be built from latches?

Not from single latches, because a transparent latch would let data race through multiple stages. You need edge-triggered flip-flops, or master-slave latch pairs.