PISO Shift Register

In short: A PISO (parallel-in, serial-out) shift register uses a 2:1 multiplexer in front of every flip-flop so that one control pin selects between loading all bits at once and shifting them out one bit per clock on a single wire.

Why parallel-to-serial conversion exists

Inside a chip, data lives in wide buses: 8, 32 or 128 bits moving together. Between chips, boards and cables, wires are expensive. Pins cost package area, connectors cost money, and parallel traces suffer skew, crosstalk and routing congestion. The classic fix is to send the word one bit at a time over a single line. The block that turns a bus into a bit stream is the PISO register, and its mirror image on the receiver is the SIPO shift register.

You meet PISO ideas everywhere: reading 8 push-buttons through one microcontroller pin with a 74HC165, the transmit shifter of a UART or SPI master, and the serializer at the heart of every SerDes lane in PCIe or HDMI. Interviewers love it because it tests flip-flops, muxes, control timing and a little system thinking in one question.

Architecture: a flip-flop with a mux in front

A shift register is a chain of D flip-flops sharing one clock. To make it parallel-loadable, each flip-flop gets a 2:1 mux on its D input. One mux input is the external parallel bit Di; the other is the output of the previous stage. A single control line, usually called SH/LD̅ (shift when high, load when low), drives every mux select.

The next-state equation for stage i is Qi+ = LD ? Di : Q(i+1), with the serial input of the first stage tied to 0 (or to a serial-in pin if you want to cascade registers). Because the select is synchronous, nothing happens between clock edges; the mux simply decides what the flip-flop will capture at the next rising edge.

Load mode versus shift mode

Key fact: Moving an N-bit word costs one load clock plus N-1 more shift clocks to see every bit, so serial transfer takes N cycles where a parallel bus needs just one. You trade time for pins.

Worked timing example: loading 1011

Let the data word be D3 D2 D1 D0 = 1011 and let the register shift right toward Q0 with a 0 fed into Q3. Output is taken at Q0, so the least significant bit leaves first.

• Edge 1 (load): SH/LD̅ = 0. State Q3Q2Q1Q0 becomes 1011. SOUT = 1 (this is D0).
• Edge 2 (shift): state 0101. SOUT = 1 (D1).
• Edge 3: state 0010. SOUT = 0 (D2).
• Edge 4: state 0001. SOUT = 1 (D3).
• Edge 5: state 0000. The register is empty and ready for the next load.

See the bits move

The animation below runs the same example: four bits sit in the register and slide one cell toward the output on every clock tick.

Timing and design pitfalls

The mux adds delay in front of every flip-flop, so the setup budget is Tclk-to-q + Tmux + Tsetup < Tperiod. With a 0.35 ns clock-to-Q, 0.15 ns mux and 0.1 ns setup, a 4-bit register closes comfortably at 1 GHz. The mux also hurts hold timing in the opposite direction: shift paths are flop-to-flop with almost no logic, so fast Q outputs can violate hold when clock skew is large. Static timing tools such as Synopsys PrimeTime or Cadence Tempus flag these, and the usual cure is inserting delay buffers.

Key fact: The load/shift select must meet setup to the clock like any data signal. Changing it asynchronously, or glitching it near an edge, can leave half the register loaded and half shifted.

• Asynchronous load variants. Parts like the 74HC165 load parallel data level-sensitively without a clock. Convenient on a board, but a headache for STA and scan insertion.
• Scan chains. DFT tools (Synopsys DFT Compiler, Siemens Tessent) replace flops with exactly this structure: a mux selecting functional D or scan input. A scan chain is a PISO/SIPO register in disguise.
• Cascading. Chain two 8-bit registers by feeding the SOUT of one into the serial input of the next to build a 16-bit stream.

Verilog in a few lines

always @(posedge clk) begin
  if (!sh_ld_n) q <= d;           // load
  else          q <= {1'b0, q[3:1]}; // shift right
end
assign sout = q[0];

Synthesis tools map this onto a flop with a mux, or onto a scan-style flop cell if the library offers one. If you want to practise this style of RTL, the shift register applications guide covers UART and SPI transmitters, and our CourseTron courses include guided labs. For teams who need production-quality serializers and clock-domain handling, Avecas design services provides RTL-to-GDS expertise, and ChipXpert VLSI training offers hands-on programmes.

Ready to go deeper? Join the CourseTron Digital Electronics course for sequential-circuit labs, timing exercises and interview practice. Explore the courses.

Frequently asked questions

What is the difference between PISO and SIPO?

PISO accepts a whole word in one clock and emits it bit by bit, while SIPO receives bits one at a time and presents them together on parallel outputs. They are paired in serial links.

How many clocks does a PISO need to send an N-bit word?

One clock to load plus N-1 clocks to expose the remaining bits, so N cycles in total for the data to appear, and an extra edge if you count flushing the register.

Which bit leaves first?

It depends on the wiring. Shifting toward Q0 and tapping Q0 sends the LSB first (as UART does); shifting left and tapping the MSB sends the MSB first (as SPI mode usually does).

Why does a PISO need a multiplexer?

Each flip-flop has only one D input, but it must accept either parallel data or its neighbour's value. The mux chooses between them under control of one shared signal.