XOR Gate

In short: The XOR (exclusive-OR) gate outputs logic 1 only when its two inputs differ, giving it the Boolean expression Y = A⊕B = A'B + AB' — a property that makes it the arithmetic heart of adders, the workhorse of parity generators, and a one-bit inequality detector in comparators.

Of the seven standard logic gates, the XOR gate is the one students most often underestimate. AND and OR behave like the English words they are named after, but XOR encodes a subtler idea — "one or the other, but not both" — and that single idea reappears everywhere from a 64-bit adder in a CPU datapath to the CRC check on an Ethernet frame. Understanding XOR deeply is one of the fastest ways to make the leap from memorising truth tables to actually reasoning about digital circuits.

The truth table and what "exclusive" means

XOR takes two inputs, A and B, and asserts its output when exactly one of them is high. Compare it to the inclusive OR you already know: OR is satisfied by the case A = B = 1, XOR deliberately excludes that case. That exclusion is the whole point, and it is why the gate reads 1 precisely when the inputs disagree.

Mnemonic: XOR is a difference detector. Feed it two bits and it returns 1 if and only if they are unequal. This is also why A⊕A = 0 and A⊕0 = A — facts you will use constantly.

Symbol and Boolean expression

The IEEE/ANSI distinctive-shape symbol for XOR is an OR gate (the curved shield) with an extra concave line across the inputs. The algebraic symbol is ⊕, and the sum-of-products form drops straight out of the two rows where the output is 1:

Y = A⊕B = A'·B + A·B'

Three identities are worth committing to memory because synthesis tools and exam questions both lean on them:

• Self-inverse: A⊕A = 0, and A⊕A' = 1.
• Identity element: A⊕0 = A (XOR with 0 is a buffer), while A⊕1 = A' (XOR with 1 is a controllable inverter).
• Associativity: A⊕B⊕C can be grouped either way, which lets you cascade 2-input gates into a multi-input parity tree.

That "controllable inverter" behaviour — one input chooses whether the other passes through straight or complemented — is exactly how XOR earns its keep inside adders and scramblers.

XOR in adders: the arithmetic core

Binary addition of two bits produces a sum and a carry. Look at the sum column alone: 0+0=0, 0+1=1, 1+0=1, 1+1=0 (carry out). That sum column is the XOR truth table, while the carry is a plain AND. A half adder is therefore nothing more than one XOR and one AND gate:

• Sum = A⊕B
• Carry = A·B

A full adder extends this to three inputs (A, B, and carry-in): Sum = A⊕B⊕Cin. When you build a 32-bit ripple-carry adder in a Verilog RTL and run it through Synopsys Design Compiler or Cadence Genus, the synthesised netlist is dense with XOR cells on the sum path precisely because of this identity. Timing-closure engineers care because the XOR chain on the sum, together with the carry chain, usually sits on the critical path, which is why faster architectures such as carry-lookahead and carry-save adders exist.

A single-bit full-adder sum needs a 3-input XOR (A⊕B⊕Cin). In a standard-cell library this is often a dedicated XOR3 cell rather than two cascaded XOR2 gates, because the single cell has lower delay and area.

XOR in parity generation and error detection

Because XOR is associative, cascading it across N bits produces the parity of the word — a 1 when the number of set bits is odd, a 0 when it is even. One XOR tree is therefore both a parity generator (compute the bit before transmission) and a parity checker (re-compute at the receiver and XOR against the received parity bit; a nonzero result flags a single-bit error).

This scales far beyond a single parity bit. Cyclic redundancy checks (CRC) used in Ethernet, USB and storage controllers are built entirely from XOR gates and shift registers implementing polynomial division in GF(2), where addition is XOR. Linear-feedback shift registers (LFSRs) for pseudo-random pattern generation in scan-based DFT — the kind Siemens Tessent or Synopsys TestMAX insert — likewise rely on XOR feedback taps. The lesson: whenever a design needs "odd/even" counting or modulo-2 arithmetic, an XOR network is the natural hardware.

XOR in comparators

A magnitude or equality comparator must decide whether two buses are identical. Since A⊕B = 0 exactly when A = B, a bitwise XOR followed by a NOR gives a clean one-bit equality flag. For an N-bit comparator you XOR each bit pair and OR the results: if any XOR fires, the words differ. The complement (an XNOR, the "equivalence" gate) is often used instead because it outputs 1 for equal bits, letting you AND the lane outputs to assert full equality directly.

This is why XOR/XNOR cells cluster in the equality-check logic of address decoders, cache tag comparators and bus-match detection. For a deeper tour of how all the primitive gates combine, see our companion piece on logic gates, and for the arithmetic that follows, our walkthrough of the half adder and full adder.

Building XOR from other gates

XOR is not a true primitive the way NAND and NOR are — but it is derivable. From the SOP expression A'B + AB' you can build it with inverters, AND and OR gates (5 gates), or, more economically for CMOS, from four NAND gates. In a real standard-cell library the gate is implemented as an optimised transmission-gate or pass-transistor structure using roughly 8–12 transistors, far cheaper than the naive gate-level schematic suggests. When you need a custom cell, teams like Avecas VLSI design services characterise these XOR/XNOR cells for timing and power before they ever reach a production library.

Want to design, simulate and synthesise gates like this hands-on? The CourseTron Digital Electronics & VLSI track takes you from truth tables to tapeout-ready RTL. For live instructor-led VLSI training, explore ChipXpert's VLSI programs.

Frequently asked questions

What is the difference between OR and XOR?

OR (inclusive-OR) outputs 1 whenever at least one input is high, including the case where both are high. XOR (exclusive-OR) excludes that last case: it outputs 1 only when the inputs differ, so A=B=1 gives 0.

Why is XOR used in adders?

The sum bit of binary addition follows the XOR truth table exactly (1+1 sums to 0 with a carry). A half adder is one XOR for the sum and one AND for the carry; a full adder computes Sum = A⊕B⊕Cin.

Is XOR a universal gate?

No. NAND and NOR are the universal gates because any function can be built from them alone. XOR cannot produce a constant 1 or implement AND/OR without help, so it is not universal — though it is indispensable for arithmetic and parity.

What is the Boolean expression for a 2-input XOR?

Y = A⊕B = A'·B + A·B'. Equivalently it can be written as (A+B)·(A·B)', and it equals the modulo-2 sum of the two bits.