In short: A logic-gate truth table enumerates every possible input combination (2ⁿ rows for n inputs) and lists the resulting output, giving you the exact, unambiguous Boolean behaviour of AND, OR, NOT, NAND, NOR, XOR and XNOR gates used throughout digital design.
Ask any VLSI interviewer for the single most important sheet of paper in digital logic and the answer is almost always the same: the truth table. Every synthesised netlist a tool like Synopsys Design Compiler or Cadence Genus produces is, at its core, a mountain of these tiny lookup tables mapped onto standard cells. Get the seven gates below into muscle memory and you can read a schematic, debug a simulation waveform, or hand-check a Karnaugh map without hesitation. This reference lays out all of them, explains why each behaves as it does, and shows where they show up in real silicon.
What a Truth Table Actually Is
A truth table is an exhaustive enumeration. For a gate with n inputs there are exactly 2ⁿ input combinations, so a 2-input gate has 4 rows, a 3-input gate has 8, and a 4-input gate 16. Each row pins one output value, so the table is a complete functional specification — there is no "undefined" case left over. This completeness is exactly why formal-verification engines (Synopsys Formality, Cadence Conformal) can prove two circuits equivalent: they compare truth tables, not gate shapes.
Key fact: Convention is that 0 = logic low (near 0 V) and 1 = logic high (near VDD, e.g. 0.8 V on a 7 nm node). This is "positive logic." The same transistor network read with the opposite convention gives a different gate — a physical NAND structure behaves as a NOR in negative logic.
The Three Basic Gates: AND, OR, NOT
These three form a functionally complete set — any Boolean function can be built from them. AND outputs 1 only when all inputs are 1 (logical multiplication). OR outputs 1 when at least one input is 1 (logical addition). NOT (the inverter) simply flips its single input.
| A | B | AND (A·B) | OR (A+B) | A | NOT (Ā) |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | — | — |
| 1 | 1 | 1 | 1 | — | — |
A quick sanity check for interviews: an AND row is 1 in only 1/2ⁿ cases, an OR row is 0 in only 1/2ⁿ cases. For a 3-input AND, exactly one of eight rows is high. If you see a standard cell named AND3 in a Liberty (.lib) file, this is precisely the function it characterises.
The Universal Gates: NAND and NOR
NAND and NOR are called universal because each one alone can implement every other gate. That is not academic trivia: in real CMOS, NAND and NOR are the natural primitives. A static CMOS NAND needs just 4 transistors (2 PMOS in parallel, 2 NMOS in series), and because NMOS pulls down faster than PMOS pulls up, NAND is usually the faster, denser choice. Synthesis tools lean heavily on NAND trees for exactly this reason.
| A | B | NAND | NOR |
|---|---|---|---|
| 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
Notice NAND is simply the AND column inverted, and NOR is the OR column inverted — the bubble on the schematic symbol literally means "invert the output." To build an inverter from a NAND, tie both inputs together: NAND(A,A) = Ā. This single trick underlies the claim of universality.
Key fact: De Morgan's theorem — (A·B)' = A' + B' and (A+B)' = A'·B' — is just the observation that the NAND and NOR truth-table columns can be re-derived from OR/AND of the inverted inputs. Tools use this constantly to "push bubbles" during technology mapping.
The Exclusive Gates: XOR and XNOR
XOR (exclusive-OR) outputs 1 when the inputs differ; XNOR outputs 1 when they are equal. These are the arithmetic workhorses: the sum bit of a full adder is A ⊕ B ⊕ Cin, and XNOR is the building block of equality comparators and parity checkers. A 32-bit comparator in an ALU is essentially 32 XNORs feeding one big AND.
| A | B | XOR (A⊕B) | XNOR |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
A useful mental model: XOR is a controlled inverter. When B = 0, Y = A; when B = 1, Y = Ā. That is why XOR appears in Gray-code generators and in the datapath of Siemens Questa testbenches that toggle bits to maximise coverage.
Reading and Verifying Tables in a Real Flow
When a gate-level simulation in Siemens ModelSim or Synopsys VCS reports a mismatch, the first debug step is to freeze the inputs at the failing cycle and hand-evaluate the gate against its truth table. If the waveform shows A = 1, B = 0 into a cell your netlist calls NAND2_X1 and the output is 0, you have found either a swapped net or a mis-mapped cell — the table says it must be 1. This is also how you sanity-check a Karnaugh-map minimisation before trusting it. For a deeper walkthrough of how these gates combine into adders and multiplexers, see our companion piece on logic gates and the follow-on guide to Boolean algebra laws.
Key fact: A full 2-input truth table has 4 rows, but the number of distinct 2-input Boolean functions is 2^(2²) = 16. The seven gates here plus their trivial cousins (buffer, constants, implication) span that whole space — which is why every cell library is, at root, a curated subset of those 16 functions.
Teams that design custom silicon, such as the engineers at Avecas VLSI design services, characterise each of these cells across process, voltage and temperature corners so the truth-table function holds even when timing shifts. The logic never changes; only the delay does.
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Frequently Asked Questions
Why are NAND and NOR called universal gates?
Because any Boolean function — and therefore any other gate — can be built using only NAND gates, or only NOR gates. Tying a NAND's inputs together gives an inverter, and from an inverter plus NAND you can reconstruct AND, OR, XOR and the rest. CMOS favours them because they are the simplest static structures to build in transistors.
How many rows does a truth table have?
Exactly 2ⁿ rows, where n is the number of inputs. A 2-input gate has 4 rows, a 3-input gate has 8, and a 4-input gate has 16. The table is complete — every possible input combination is listed.
What is the difference between XOR and OR?
OR outputs 1 when at least one input is 1, including the case where both are 1. XOR (exclusive-OR) outputs 1 only when the inputs differ, so the "both are 1" row is 0. XOR is the odd/even (parity) detector; OR is the "any" detector.
Do truth tables change with technology node?
No. A gate's truth table is its logical function and is independent of the process node. Moving from 28 nm to 7 nm changes transistor count, delay and power, but a NAND stays a NAND. Only timing and physical characterisation differ.