4 to 2 Encoder

In short: A 4-to-2 encoder turns a one-hot 4-line input into a 2-bit binary code using just two OR gates (Y1 = D2 + D3, Y0 = D1 + D3), but it silently gives wrong answers when more than one input is high or when all are low, which is why real designs use a priority encoder with a valid flag.

What an encoder actually does

A decoder expands a small binary number into many lines; an encoder does the reverse. It watches several input lines, assumes that exactly one of them is active, and reports the index of that line as a binary number. A 4-to-2 encoder has four inputs (D0 to D3) and two outputs (Y1, Y0). If D2 is high, the output is 10, because 2 in binary is 10.

The key phrase is "assumes exactly one". The basic encoder has no way to check that assumption, and nearly every interview question on this block is really a question about what happens when the assumption breaks. If you have not yet seen the opposite block, read our 2-to-4 decoder guide first; the two are mirror images.

The truth table

Only four of the sixteen possible input combinations are "legal" one-hot patterns. The rest are the problem.

Key fact: 12 of the 16 input combinations never appear in the truth table. They are don't-cares for the minimiser, but in real hardware they can and do occur, and the circuit still produces some output for them.

Deriving the equations

Read the table column by column. Y1 is 1 whenever D2 or D3 is the active line, so Y1 = D2 + D3. Y0 is 1 when D1 or D3 is active, so Y0 = D1 + D3. Notice that D0 appears in neither equation: index 0 is encoded by the absence of any other signal. This is the root of the first problem, covered below.

Because we treat the twelve illegal rows as don't-cares, a Karnaugh map collapses to these two-term ORs with no inversions. That is why the encoder costs only two 2-input OR gates, roughly 12 transistors in static CMOS (a NOR plus inverter per gate, 6 transistors each), which is tiny.

Problem one: D0 and "nothing" look identical

With D0 = 1 and all others 0, the outputs are 00. With every input 0, the outputs are also 00. A downstream block cannot tell "line 0 fired" from "no line fired". In an interrupt controller that distinction is critical: you would service a phantom interrupt 0 whenever the bus is idle.

Key fact: The fix is an extra output, usually called V (valid) or GS (group select), equal to D0 + D1 + D2 + D3. Output code 00 is trusted only when V = 1.

Problem two: multiple inputs high

Suppose D1 and D2 are both high. Y1 = 1 + 0... precisely, Y1 = D2 + D3 = 1 and Y0 = D1 + D3 = 1, so the output is 11, which claims D3 is active. Nothing in the circuit is broken; the OR gates simply merge the codes of 01 and 10. Likewise D0 and D3 together give 11, and D1 and D2 and D3 together still give 11.

The output is the bitwise OR of the individual codes. That is a mathematically clean description and an easy interview answer: the plain encoder returns the OR of the codes of all asserted inputs, which is meaningless unless exactly one is asserted.

Watching it work: animated walk-through

The animation below raises one input at a time and shows the legal outputs. Each step lasts one second.

The fix: priority encoding

A priority encoder defines what should happen when several inputs are high: the highest-numbered active line wins. With D3 as highest priority, the equations become Y1 = D2 + D3 and Y0 = D3 + D1·D2', since D1 only counts when D2 is low. Now D1 and D2 together give 10 (D2 wins), which is a defensible, deterministic answer. Add V = D0 + D1 + D2 + D3 and every input pattern has a meaning.

• Interrupt controllers: the lowest-numbered request is often the most urgent, so the priority direction is a spec decision, not a law.
• Arbiters: a priority encoder can starve low-priority requesters, so fairness needs extra logic such as round-robin.
• Cascading: larger encoders are built by chaining 4-input stages with an enable-in and group-signal output, the idea we expand in the 8-to-3 encoder article.

In RTL and in the tools

In Verilog, a priority encoder is naturally written with an if / else if chain, which synthesis tools such as Synopsys Design Compiler or Cadence Genus map to the AND-OR structure above. Be careful with case on a one-hot input: a missing default creates an inferred latch, and a casez with wildcards gives priority behaviour that simulators and synthesis may interpret differently if you also add full_case/parallel_case pragmas. Questa and VCS lint will flag these mismatches.

always @* begin
  v = |d;
  if      (d[3]) y = 2'b11;
  else if (d[2]) y = 2'b10;
  else if (d[1]) y = 2'b01;
  else           y = 2'b00;
end

If you ever need this at scale, such as a 64-request arbiter, the delay of a long priority chain matters. Teams that design such blocks professionally, for example the design services group at Avecas, restructure the chain into a tree to cut logic depth from linear to logarithmic.

Key fact: Encoders are also used inside flash ADCs: a thermometer-code comparator bank is reduced to binary by an encoder, where bubble errors are exactly the multiple-input problem in analogue clothing.

Interview checklist

• State the equations from memory: Y1 = D2 + D3, Y0 = D1 + D3.
• Explain the D0 ambiguity and name the valid bit.
• Explain multiple inputs as the OR of codes, then give the priority fix.
• Contrast with a decoder, and know how it feeds a priority encoder design.

Want to practise this on real tools and get placement-ready? Explore the CourseTron courses, or look at hands-on VLSI training at ChipXpert.

Ready to master digital design? Join the CourseTron Digital Electronics course and build encoders, decoders and arbiters with guided labs and interview practice.

FAQ

Why does a 4-to-2 encoder need only two OR gates?

Each output bit is 1 for exactly two of the four legal inputs, and the other rows are don't-cares, so each output is a simple OR of two inputs.

What happens if all inputs of a 4-to-2 encoder are 0?

The outputs are 00, the same as when D0 is the active input. A valid output signal is needed to tell the two cases apart.

How does a priority encoder differ from a simple encoder?

A priority encoder picks one winner (usually the highest index) when several inputs are high and normally provides a valid flag, so every input pattern has a defined result.

Is an encoder combinational or sequential?

Combinational. The outputs depend only on the present inputs and there is no memory element.