2 to 4 Decoder

In short: a 2-to-4 decoder uses two address bits (and usually an enable) to raise exactly one of four output lines, built from four AND gates (active-high) or four NAND gates (active-low) fed by the true and complemented inputs.

What a 2-to-4 decoder actually does

A decoder converts an n-bit binary code into a one-hot pattern on 2ⁿ lines. With n = 2 you get four lines, and each of the four input combinations 00, 01, 10, 11 selects precisely one of them. Think of it as the hardware version of a switch statement: the address is the case value, and the output wire is the branch that fires.

It is the smallest useful decoder, and it shows up everywhere: chip-select logic that picks one of four peripherals, the row or column pre-decoder in a small SRAM, the bank-select logic in a memory controller, and the first stage of every larger decoder. Interviewers love it because the whole design fits on a whiteboard, yet it exposes whether you understand minterms, polarity and enable logic.

The truth table, with enable

Real decoders carry an enable input. When E = 0 the device is deselected and every output sits at its inactive level, which is what lets you cascade or bus-share decoders. Active-high outputs are written Y_n, active-low outputs are written with a bar or an _n suffix.

Each active-high output is exactly one minterm of the address bits: Y0 = E·A1'·A0', Y1 = E·A1'·A0, Y2 = E·A1·A0', Y3 = E·A1·A0. No Karnaugh map is needed because no two minterms ever combine.

Deriving the gate-level circuit

Because every output is a single product term, the implementation is mechanical. You need two inverters to produce A1' and A0', and four AND gates, each taking one choice of polarity for each address bit. With an enable, each AND becomes three-input. That is 2 inverters plus 4 three-input ANDs: roughly 8 to 10 gate equivalents, with a worst-case path of one inverter plus one AND.

Active-high versus active-low outputs

Polarity is not cosmetic. An active-high decoder asserts its selected line to logic 1, so the selected output is the only 1. An active-low decoder asserts its selected line to 0 and parks the other three at 1. To build the second kind you replace each AND with a NAND, so Y0_n = (E·A1'·A0')'. In CMOS this is the cheaper option too: a NAND is a single stage, while an AND is a NAND followed by an inverter, so the NAND form is faster and smaller.

Why do real parts favour active-low? Chip-select and output-enable pins on memories, UARTs and ADCs are almost always active-low, so an active-low decoder drives them directly with no inverter. Open-drain buses and wired-OR schemes also pull a line low to assert it, which keeps idle lines at a defined high via pull-ups. The classic dual 2-to-4 part, the 74HC139, has active-low outputs and an active-low enable. Its 3-to-8 sibling, the 74HC138, follows the same convention, which we cover in the 3-to-8 decoder article.

An active-low output is just the active-high output inverted. Swapping polarity never changes which line is selected, only the voltage level that means "selected".

A common bug is mixing the two: wiring an active-low Y1_n into a block that expects active-high will select every other device and deselect the right one. Always read the bubble on the symbol, and name nets with an _n or # suffix so the polarity survives through schematic, RTL and constraint files.

See it in motion

Describing it in RTL and what synthesis does

In Verilog you rarely instantiate gates. You write intent, and the synthesis tool maps it. Design Compiler, Genus and Vivado all reduce this to the same handful of cells.

module dec2to4 (
  input  wire [1:0] a,
  input  wire       en,
  output reg  [3:0] y     // active-high
);
  always @* begin
    y = 4'b0000;
    if (en) y[a] = 1'b1;
  end
endmodule
// active-low: assign y_n = ~y;

The default assignment before the if is the important detail: it prevents an inferred latch when en is low. Equivalent single-line forms such as y = en ? (4'b1 << a) : 4'b0 synthesise identically. In a standard-cell flow the active-low version usually maps to four NAND3 cells plus two inverters, and the final inversion in ~y is absorbed into the NAND, so describing it as a separate inverter costs nothing after optimisation. Equivalence checkers such as Synopsys Formality and Cadence Conformal will confirm both forms match. If you want to practise this flow with real tool exercises, our combinational logic design guide walks through it, and Avecas design services applies the same fundamentals on production chips.

Using decoders: enables, cascading and logic synthesis

• Address decoding: the two upper bits of a small address bus select one of four 16 KB regions; the lower bits go straight to each device.
• Cascading: feed A2 into the enable of two 2-to-4 decoders (one through an inverter) and you get a 3-to-8 decoder. Four decoders plus one more make a 4-to-16.
• Function generator: a decoder plus an OR gate implements any function of its inputs. A 2-to-4 decoder with an OR of Y1 and Y2 is an XOR of A1 and A0.
• Demultiplexer: use E as the data input and the address as the select, and a decoder becomes a 1-to-4 demux.

Decoder with enable = demultiplexer. The data line enters through E, and the address chooses where it comes out. That identity is a frequent interview follow-up.

Common mistakes and interview traps

• Forgetting that E = 0 forces all outputs inactive, and that "inactive" means 1 for an active-low part.
• Glitches: when the address changes from 01 to 10 both bits move, and unequal path delays can briefly assert Y0 or Y3. Never use raw decoder outputs as asynchronous clocks or resets; register them first.
• Counting gates wrongly. The full circuit with enable is 2 inverters and 4 three-input gates, not 4 two-input gates.
• Missing the minterm connection: asked "which gate drives Y2?", answer with E·A1·A0', not just "an AND".

To go deeper on cascading and the 74HC138 pinout, read the 3-to-8 decoder walkthrough, then practise timing and glitch analysis on real netlists in the CourseTron course catalogue. For hands-on instructor-led VLSI practice, ChipXpert's VLSI training programmes take these building blocks through synthesis and physical design.

Ready to master combinational and sequential design with guided labs and quizzes? Explore the Digital Electronics track in the CourseTron courses and start building circuits today.

FAQ

How many outputs and gates does a 2-to-4 decoder have?

It has four outputs. With an enable, it needs two inverters and four three-input AND gates (or NAND gates for active-low outputs).

What is the difference between active-high and active-low decoder outputs?

An active-high decoder drives the selected output to 1 and all others to 0. An active-low decoder drives the selected output to 0 and all others to 1. Only the voltage convention differs; the same line is selected.

Why are decoder outputs usually active-low in real chips?

NAND-based outputs are faster and smaller in CMOS, and most chip-select and enable pins on memories and peripherals are active-low, so no extra inverters are needed.

How do you build a 3-to-8 decoder from 2-to-4 decoders?

Use two 2-to-4 decoders. Connect A2 to the enable of one directly and to the other through an inverter, and share A1 and A0 between them.