3 to 8 Decoder

In short: A 3-to-8 decoder turns a 3-bit code into one active line out of eight, you can build it from two 2-to-4 decoders by letting the top bit A2 switch their enables, and because every output is a minterm, an OR (or NAND) of selected outputs implements any 3-variable Boolean function.

A 3-to-8 decoder is one of those blocks you meet in the first week of digital design and keep meeting for a career. It drives chip-select lines, expands opcode fields, and generates minterms. Here you will derive it, build it hierarchically from two 2-to-4 decoders, and then use it to implement a full adder, which is a favourite interview question.

What a 3-to-8 decoder actually does

The block has three data inputs A2, A1, A0 (A2 is the most significant bit), an enable EN, and eight outputs Y0 to Y7. When EN is high, exactly one output goes high: the one whose index equals the binary value of the input. Input 101 raises Y5 and leaves the other seven low. When EN is low, all outputs stay low. This pattern is called one-hot encoding.

Each output is therefore a single product term: Y5 = A2 · A1' · A0 · EN, and Y0 = A2' · A1' · A0' · EN. In general, an n-to-2ⁿ decoder needs 2ⁿ product terms, one per minterm. If you have already worked through the 2-to-4 decoder, this is the same idea with one extra variable and twice as many outputs.

Key fact: A decoder is a minterm generator. Output Yk equals minterm mk of the inputs, which is exactly why decoders can implement arbitrary logic.

Building it from two 2-to-4 decoders

Look at the codes in binary. Values 000 to 011 all have A2 = 0, and values 100 to 111 all have A2 = 1. So the top bit only chooses which half of the output range is live, and the lower two bits choose the line within that half. That is precisely the job of a pair of 2-to-4 decoders with enable inputs.

• Decoder U0 handles the low half. Its enable is A2', so it is awake only when A2 = 0, and its outputs become Y0 to Y3.
• Decoder U1 handles the high half. Its enable is A2 directly, and its outputs become Y4 to Y7.
• A1 and A0 are wired to the data inputs of both decoders in parallel.

Work one case. For A2A1A0 = 110, A2 = 1 so U1 is enabled and U0 is forced to all zeros. Inside U1, A1A0 = 10 selects output O2, which is global line Y(4 + 2) = Y6. The general rule is Y(4·A2 + k), where k is the local index.

The same trick scales. A 4-to-16 decoder needs four 2-to-4 decoders for the low bits plus a fifth one that decodes the top two bits and drives the four enables. A 5-to-32 decoder uses four 3-to-8 devices and one 2-to-4. Parts like the 74HC138 (3-to-8) and 74HC139 (dual 2-to-4) were designed for exactly this cascading, and both use active-low outputs and enables, so on a real board you swap the polarities: the low-half enable pin sees A2, and the high-half pin sees A2'.

Watch it decode

The animation steps the input through all eight codes. Notice that the lit row moves one position per step and that no two rows are ever lit together. That mutual exclusivity is the property the rest of your system relies on, for example when only one peripheral may drive a shared bus.

Implementing Boolean functions with a decoder

Since every output is a minterm, writing a function in sum-of-minterms form tells you which outputs to combine. Take the full adder with inputs A, B and carry-in Cin. Its sum is 1 for input codes 001, 010, 100 and 111, and its carry-out is 1 for 011, 101, 110 and 111:

• Sum = Σm(1, 2, 4, 7)
• Cout = Σm(3, 5, 6, 7)

Connect A, B, Cin to A2, A1, A0, tie EN high, then feed Y1, Y2, Y4, Y7 into one 4-input OR gate and Y3, Y5, Y6, Y7 into another. Output Y7 is shared by both gates, because 111 produces both a sum of 1 and a carry of 1. You can sanity-check it: 1 + 1 + 0 gives code 110, which lights Y6, which feeds only the carry OR, giving Sum = 0 and Cout = 1. Correct.

If your decoder has active-low outputs, as the 74HC138 does, use De Morgan's theorem. A NAND of active-low lines equals the OR of the corresponding minterms, so the textbook solution is a 74HC138 plus a 74HC20 dual 4-input NAND. The cost is two chips for an adder bit, which is why nobody builds adders this way in practice, but it is the cleanest demonstration of the technique.

Key fact: With an active-low decoder, F equals the AND of the active-low lines for the minterms where F is 0. If F has more than four minterms, wire up the zeros instead of the ones and you need a smaller gate.

Choosing an implementation

One honest observation: after synthesis the hierarchical and flat versions usually converge to the same netlist, because the tool flattens the hierarchy and shares the inverters. The structural choice matters most on a breadboard or in an interview whiteboard, and when you need to reuse a decoder block.

There is one real electrical consequence. A2' arrives one inverter delay after A2, so during a transition such as 011 to 100, U0 may switch off slightly after U1 switches on, or the reverse. Decoder outputs can glitch for a few gate delays. Never use a raw decoder output as a clock or a write strobe without qualifying it with an enable or registering it.

In RTL and in silicon

In practice you describe the behaviour and let the tool pick the gates:

module dec3to8 (
  input  logic [2:0] a,
  input  logic       en,
  output logic [7:0] y
);
  always_comb begin
    y = '0;
    if (en) y[a] = 1'b1;
  end
endmodule

Synopsys Design Compiler or Cadence Genus maps this onto standard cells such as AND3 and NOR gates, usually merging it with downstream logic. On an FPGA, Vivado treats each output as a 3-input function that fits in a LUT, so the whole decoder costs about eight LUT inputs worth of logic. Equivalence checkers such as Synopsys Formality or Siemens Questa tools confirm that a hand-built two-decoder version matches this behavioural one. If you want to see how such blocks go from RTL to layout, the physical design programs at ChipXpert VLSI training walk through that flow end to end.

Interview traps to avoid

• Forgetting which signal feeds which enable. The enable of the low-half decoder takes the complement of A2.
• Counting decoders for larger sizes: 5-to-32 takes four 3-to-8 plus one 2-to-4, not eight.
• Mixing polarities. If outputs are active-low, the OR becomes a NAND.
• Missing the demultiplexer view: feed data into EN and the same circuit routes it to one of eight outputs. Compare this with a multiplexer used as universal logic, which solves the same function-implementation problem from the opposite direction.

Want to practise decoders, encoders, multiplexers and full combinational design with guided exercises? Join the CourseTron digital electronics track and browse all CourseTron courses.

Frequently asked questions

How many 2-to-4 decoders do I need for a 3-to-8 decoder?

Two, plus one inverter for A2. Each 2-to-4 decoder needs an enable input, which carries the A2 selection.

What is the difference between a decoder and a demultiplexer?

They are the same circuit. A decoder uses the enable as a control, while a demultiplexer treats the enable as a data input and routes it to the output chosen by the select lines.

Can a 3-to-8 decoder implement any 3-variable function?

Yes. Connect the variables to the inputs and combine the outputs for the minterms of the function with an OR gate, or a NAND gate for active-low outputs.

Why do real decoder ICs use active-low outputs?

Most chip-select and enable pins in digital systems are active-low, and TTL-style outputs sink current more strongly than they source it, so the convention stuck.