8 to 3 Encoder

In short: An 8-to-3 (octal-to-binary) encoder takes eight input lines, of which exactly one is expected to be high, and outputs the 3-bit binary index of that line using just three 4-input OR gates: A2 = D4+D5+D6+D7, A1 = D2+D3+D6+D7, A0 = D1+D3+D5+D7.

What an 8-to-3 encoder actually does

A decoder expands a small binary code into a one-hot line. An encoder does the reverse: it compresses a one-hot set of lines back into a compact code. The 8-to-3 encoder has eight inputs, D0 to D7, and three outputs, A2 A1 A0. When line D5 goes high, the outputs read 101, which is 5 in binary. Hence the other name, octal-to-binary encoder.

The key assumption is that only one input is active at a time. Keyboards, rotary switches and interrupt-request lines are classic sources of such one-hot signals. If that assumption breaks, the plain encoder produces garbage, a problem we deal with later and which the priority encoder solves properly.

Key fact: An N-input encoder with one-hot inputs needs log2(N) outputs. For N = 8 that is 3 bits, so only 8 of the 256 possible input patterns are legal.

Truth table

Only the eight one-hot rows matter. Every other row of the full 2^8 table is a don't-care at best and an error at worst.

Deriving the equations

Read each output column and list the inputs for which it is 1. A2 is high for inputs 4, 5, 6 and 7, so A2 = D4 + D5 + D6 + D7. A1 is high for 2, 3, 6 and 7. A0 is high for 1, 3, 5 and 7. Notice the pattern: A0 collects every odd input, A1 collects inputs whose bit 1 is set, A2 collects inputs whose bit 2 is set.

• A2 = D4 + D5 + D6 + D7
• A1 = D2 + D3 + D6 + D7
• A0 = D1 + D3 + D5 + D7

D0 appears in no equation. When D0 is the active line the outputs are 000, which is also what you get with no input active at all. That ambiguity is a genuine design flaw, and interviewers love to ask about it.

Key fact: The whole encoder is three 4-input OR gates. Because each input fans out to at most three gates, the critical path is a single OR delay, typically well under a nanosecond in a modern standard-cell library.

Logic diagram

The schematic is just three OR gates. In a Verilog flow you would write it as three assign statements; Synopsys Design Compiler or Cadence Genus will map each to an OR4 cell, or to a NOR4 plus inverter, depending on the library's area and delay numbers.

module enc8to3 (input [7:0] d, output [2:0] a);
  assign a[2] = d[4] | d[5] | d[6] | d[7];
  assign a[1] = d[2] | d[3] | d[6] | d[7];
  assign a[0] = d[1] | d[3] | d[5] | d[7];
endmodule

Seeing it in motion

The animation below pulses D5. Follow the signal: it reaches only the A2 and A0 gates, so the output reads 101, which is 5.

Limitations and the pitfalls interviewers probe

• The D0 ambiguity. Output 000 means either D0 is active or nothing is. Real designs add a valid output, V = D0+D1+...+D7, so downstream logic can tell the difference.
• Multiple active inputs. If D3 and D6 are both high, A2 A1 A0 = 111, which falsely reports line 7. A plain OR encoder simply ORs the codes together.
• Glitches. If the inputs change between two one-hot states with skew, a momentary all-zero or double-hot state can produce a short wrong output. Registering the outputs avoids this.

The fix for the second problem is priority resolution: the highest-numbered active line wins, which turns the equations into larger logic with inhibit terms. That is the subject of our priority encoder article, and it pairs naturally with the 3-to-8 decoder, the encoder's inverse.

Key fact: The textbook 74148 is an 8-to-3 priority encoder with active-low inputs and outputs, plus enable-in, enable-out and group-signal pins so that chips can be cascaded to 16 or 64 inputs.

Synthesis and verification notes

For a design this small, synthesis is trivial, but the habits matter. Write a self-checking testbench that drives all eight one-hot patterns and compares against a reference function, then add assertions that flag any non-one-hot input pattern, using $onehot0 in SystemVerilog. Simulators from Siemens (Questa) and Synopsys (VCS) both support it. In a larger design, an encoder like this typically sits inside an interrupt controller, where hardening the one-hot assumption with assertions catches integration bugs early. If you are building such blocks professionally, Avecas design services handle RTL-to-GDS work, and ChipXpert offers hands-on VLSI training.

To go further, work through the full path in our digital electronics courses.

Ready to practise? Join the CourseTron Digital Electronics course for guided Verilog labs, quizzes and interview drills on encoders, decoders and combinational design.

FAQ

Why does an 8-to-3 encoder need only OR gates?

Each output bit is 1 for a fixed set of input indices. Because only one input is high at a time, the output is simply the OR of all inputs in that set, so no AND or NOT gates are needed.

What is the difference between an encoder and a priority encoder?

A plain encoder assumes exactly one active input. A priority encoder gives a defined output when several inputs are high by choosing the highest-priority one, and usually adds a valid flag.

How many 4-input OR gates are needed?

Three: one each for A2, A1 and A0. Each gate takes four of the data inputs, and D0 is unused.

What does output 000 mean?

It is ambiguous: either D0 is active or no input is active. Add a valid output or use a priority encoder with a group-select signal to distinguish them.