Priority Encoder

? Print / Save as PDF

In short: A priority encoder outputs the binary index of the highest-priority active input and adds a valid flag, so it never produces garbage when several inputs are high or none are.

Why a plain encoder is not enough

A basic 4-to-2 encoder assumes exactly one input is high at any time. That assumption is fine in a textbook, but real hardware breaks it constantly. Two keys pressed together, two devices raising interrupts in the same clock cycle, or two bus masters requesting a grant all produce multiple active inputs. If you feed 0110 into a plain OR-based encoder, you get 11 at the output, which names an input that was never asserted. The result is a wrong interrupt vector, a wrong grant, a wrong key.

A priority encoder fixes this by defining a ranking. When more than one input is active, only the highest-ranked one is encoded and the rest are ignored. It also solves a second ambiguity: an all-zero input and an input of D0 alone both give output 00 in a plain encoder. The extra valid output removes that confusion.

The 4-input truth table

Take D3 as the highest priority and D0 as the lowest. Outputs are Y1 Y0 plus a valid bit V. An "x" means don't-care: the value has no effect on the result.

Key fact: five rows cover all 16 input combinations. Don't-cares collapse the table, which is exactly why the logic stays tiny.

Notice that when V = 0, Y1 and Y0 are meaningless. Downstream logic must qualify the encoded value with V, otherwise it will treat "nothing requested" as "request 0".

Deriving the Boolean equations

Read each output directly from the table:

• Y1 = D3 + D2. The upper bit is 1 whenever the winner is index 2 or 3.
• Y0 = D3 + D2'·D1. The lower bit is 1 for index 3, or for index 1 when D2 is not overriding it.
• V = D3 + D2 + D1 + D0. At least one request is active.

Look at Y0: D2' is the priority mask. It blocks D1 from influencing the output when a higher input exists. D3 does not need masking in Y0 because it already forces 1. This pattern, where each lower input is gated by the complement of every higher one, generalises to any width.

Watch it resolve a conflict

The animation below cycles through three cases: D1 alone, D1 and D2 together, then D3 with everything else. Watch the winner change only when a higher input arrives.

Cascading to wider encoders

Real systems need 8, 16 or 64 inputs. You do not rewrite the equations; you cascade. The classic 74148 is an 8-to-3 priority encoder with active-low inputs and outputs, an enable input EI, an enable output EO and a group-select output GS. To build a 16-input encoder, you use two 74148s: the high-priority chip's EO drives the low chip's EI, so the lower chip only works when the upper one sees no requests. GS from each chip acts as the valid flag and supplies the extra output bit.

Key fact: with active-low parts, "no request" is all-ones. Mixing polarities between cascaded stages is the most common wiring bug on a breadboard and in a netlist.

In RTL you rarely instantiate such parts. You write a loop instead and let synthesis do the work.

always @* begin
  valid = |d;
  y = 2'b00;
  for (i = 0; i < 4; i = i + 1)
    if (d[i]) y = i[1:0];   // last match = highest priority
end

The loop works because later iterations overwrite earlier ones, so the highest set index wins. Tools such as Synopsys Design Compiler, Cadence Genus and Siemens Precision map this to the same few gates, or to a faster tree for large widths. Be careful with casez and unique case: if you mark a case statement as parallel when overlapping patterns exist, simulation and synthesis can disagree, a classic interview trap.

Use in interrupt controllers

The most important application is arbitration of interrupt requests. Suppose eight peripherals raise IRQ0 to IRQ7. The controller latches pending requests, masks the disabled ones, and feeds the result to a priority encoder. The encoded index becomes the interrupt vector or the offset into the vector table, and V becomes the INT line to the CPU. Legacy designs like the Intel 8259 PIC work on this principle, and modern ones such as the ARM GIC and RISC-V PLIC extend it with programmable priorities, per-source thresholds and many more sources.

Concrete example: UART (IRQ5) and timer (IRQ2) fire in the same cycle. With IRQ5 ranked above IRQ2, the encoder outputs 101 and V = 1. The CPU services the UART, clears it, and the encoder then outputs 010 for the timer. No request is lost, because the lower one stays pending until it becomes the winner.

Design pitfalls and interview angles

• Fairness: fixed priority can starve low-ranked sources. Arbiters for bus access often use round-robin or rotating priority instead.
• Timing: a 64-input ripple chain is slow. Synthesis builds a tree of 4- or 8-input encoders, and the critical path grows with log N rather than N.
• Glitches: if inputs arrive asynchronously, synchronise them before encoding, or the output may briefly show a wrong index.
• Verification: exhaustively test all 2^N combinations for small N. For large N, use constrained-random tests plus a formal property: the output index must equal the highest set bit.

Typical interview questions: write the equations for a 4-input priority encoder, explain why V is needed, and show how to build a 16-input encoder from 4-input ones. Related building blocks are covered in our priority arbiter design guide, and if you want structured practice with RTL and verification, see our CourseTron courses. For hands-on bootcamp training, ChipXpert runs instructor-led VLSI programmes.

FAQ

What is the difference between an encoder and a priority encoder?

A plain encoder assumes only one input is active and gives wrong results otherwise. A priority encoder ranks inputs and encodes only the highest active one, and it normally adds a valid output.

Why does a priority encoder need a valid output?

Because output 00 can mean either "D0 is active" or "no input is active". The valid bit separates the two cases.

Which input is the highest priority?

It is a design choice. By convention the highest-numbered input wins, as in the 74148, but some systems rank IRQ0 highest. Always check the datasheet or spec.

How many gates does a 4-input priority encoder need?

About six: two ORs for Y1 and V terms, an AND with an inverter and an OR for Y0, plus the final valid OR. Synthesis may share terms to reduce this.

Ready to design and verify real digital blocks? Explore the Digital Electronics and RTL design tracks in the CourseTron courses and build interrupt controllers, arbiters and more with industry tool flows.