In short: Stuck-at testing checks whether logic nodes toggle correctly by watching the chip's outputs, while IDDQ testing measures the quiescent supply current to catch physical defects (bridges, gate-oxide shorts) that leak current even when the logic output still looks right — the two methods overlap partially but each catches failures the other misses, so high-reliability flows run both.
Two fundamentally different questions
Every DFT engineer eventually learns that "does the chip pass?" is not a single question. Stuck-at and IDDQ testing answer two different ones. Stuck-at asks a logical question: if I force this net to a value and propagate it to an observable output, does the output match the fault-free simulation? IDDQ asks a physical one: when the circuit is at rest and should draw almost no current, how much current is it actually pulling from the supply rail?
Because they probe different physics, they fail on different defect populations. A gate-oxide pinhole or a resistive metal bridge can leave the Boolean function of a cell intact under one input pattern yet silently convert a 10 nA leakage budget into milliamps. Stuck-at vectors may never notice; IDDQ screams immediately. Conversely, an open via that breaks a signal path produces a clear logic error that stuck-at catches but that may not disturb quiescent current at all.
How stuck-at modeling works
The single stuck-at fault (SSAF) model is the workhorse abstraction of digital test. Each line in the gate-level netlist is assumed, one at a time, to be permanently tied to 0 (stuck-at-0) or 1 (stuck-at-1). An ATPG engine — Synopsys TetraMAX/TestMAX, Siemens Tessent, or Cadence Modus — generates a vector that activates the fault (drives the opposite value onto the line) and propagates its effect to a scan flop or primary output.
A design with N lines has roughly 2N stuck-at faults. After collapsing equivalent faults, a 5-million-instance block might carry ~12–15 million collapsed faults, and modern tools routinely report test coverage above 99%. The metric that matters is test coverage (detected / testable), not raw fault coverage, because undetectable and ATPG-untestable faults are excluded.
Stuck-at coverage above 99% does not mean zero escapes. A chip can achieve 99.3% stuck-at coverage and still ship latent bridging defects, which is exactly the gap IDDQ was invented to close in the 1980s and 1990s.
How IDDQ testing works
A fully static, well-designed CMOS gate draws current only during switching; at rest, the only supply current is subthreshold and junction leakage. In a healthy older-node design that quiescent current (IDDQ) sat in the nanoamp-to-low-microamp range. The test applies a pattern, lets the circuit settle, then measures the supply current with a precision parametric measurement unit. A defective device that creates a conductive path from VDD to VSS — a metal-to-metal bridge, a gate-oxide short, or a leaky junction — pulls current orders of magnitude higher than the fault-free baseline.
The beauty is observability: a single current measurement interrogates the entire powered-on circuit at once, so you need only a handful of well-chosen patterns (often fewer than 50–100) to sensitize a large fraction of potential bridges, versus the millions of cycles a stuck-at scan pattern set consumes.
Coverage overlap — and the gaps
The two models intersect but neither contains the other. A pseudo-stuck-at (IDDQ) fault model marks a cell as detected if a pattern drives it into a state where a defect would cause excess current. Many defects that register as stuck-at faults also cause abnormal IDDQ, which is the overlap region. But each method owns exclusive territory.
| Defect type | Stuck-at | IDDQ |
|---|---|---|
| Signal line open / broken via | Usually detected | Often missed (no leakage) |
| Gate-oxide short | Sometimes missed | Reliably detected |
| Resistive VDD–VSS bridge | Pattern-dependent | Reliably detected |
| Delay / timing-only defect | Missed (needs at-speed/transition) | Missed |
| Leaky junction / weak device | Missed | Detected |
For reliability-critical parts — automotive (ISO 26262), aerospace, medical — teams historically combined stuck-at, transition-delay and IDDQ to drive the defective-parts-per-million (DPPM) rate toward single digits. The methods are complementary, not redundant.
Why IDDQ faded at advanced nodes
Here is the catch every modern DFT engineer must know: IDDQ's whole premise is that the fault-free leakage floor is negligibly small. At 180 nm and above this held. But as geometries shrank below ~90 nm, subthreshold and gate leakage ballooned — a healthy multi-million-gate die at 7 nm can draw hundreds of milliamps of quiescent current. The defect signal drowns in the normal leakage distribution, so a flat current threshold no longer separates good from bad.
The industry responded with delta-IDDQ and current-signature / statistical methods: instead of an absolute limit, you look at the ratio or variance between successive pattern measurements, or compare a die against its wafer neighbours (nearest-neighbour residual, outlier screening). These adaptive techniques keep current-based testing useful where a fixed threshold cannot. For a deeper treatment of the measurement setup and signature analysis, see our companion piece on IDDQ testing fundamentals, and for the logic-side vectors see stuck-at fault ATPG.
Practical flow guidance
In a production test program you typically order tests by cost and coverage: scan-based stuck-at and transition-delay patterns run first because they are deterministic and diagnosable, then a short IDDQ (or delta-IDDQ) suite runs as a reliability screen. Memory BIST handles the arrays separately. Tools such as Siemens Tessent and Synopsys TestMAX generate the stuck-at and transition sets and can mark IDDQ-testable faults, letting you track pseudo-stuck-at coverage alongside the classic metric.
If you are building silicon for a demanding customer, pairing these test strategies with solid design-for-test insertion is where real yield and quality engineering happens — the kind of work that firms like Avecas VLSI design services do on production tapeouts. The takeaway for an interview: never present stuck-at coverage as a complete quality statement without acknowledging the defect classes it structurally cannot see.
Want to run real ATPG and interpret current signatures hands-on? The CourseTron DFT track walks you through scan insertion, stuck-at and transition ATPG, and modern IDDQ screening on industry tools.
Frequently asked questions
Is IDDQ testing obsolete?
Not obsolete, but transformed. Absolute-threshold IDDQ is impractical below ~90 nm because of high intrinsic leakage. Statistical variants — delta-IDDQ, current signatures and nearest-neighbour outlier screening — remain valuable reliability screens, especially for automotive and other high-reliability parts.
Can stuck-at and IDDQ detect the same defect?
Often, yes — a resistive bridge can corrupt logic for some patterns (stuck-at catch) and raise quiescent current (IDDQ catch), creating an overlap region. But each also detects defects the other cannot, which is why both are run.
How many IDDQ patterns do I need?
Far fewer than for stuck-at. Because a single current measurement observes the whole powered circuit, a carefully chosen set of tens of patterns can sensitize most potential bridge sites, versus millions of scan cycles for full stuck-at coverage.
What replaces IDDQ for catching leakage defects at advanced nodes?
A combination of statistical IDDQ (delta/signature), very-low-voltage testing, transition-delay fault testing, and cell-aware ATPG targeting realistic defect models extracted from layout.