In short: MIPI defines the thin, high-speed serial links inside almost every phone — CSI-2 carries camera pixels and DSI drives the display, both running over a D-PHY or C-PHY physical layer that trades a few low-swing differential lanes for multi-gigabit bandwidth at tiny power.
If you open any modern smartphone, the camera module and the display panel are not wired to the SoC with the dozens of parallel traces you might expect. They connect through a handful of wires defined by the MIPI Alliance. MIPI (Mobile Industry Processor Interface) is a family of specifications born out of a simple mobile constraint: pins, board area and power are scarce, but the data rates for 200 MP sensors and 120 Hz 4K panels are enormous. The answer was to move from wide parallel buses to a few serialized, low-voltage differential lanes. This article walks through the two interfaces an engineer meets first — CSI-2 (camera) and DSI (display) — and the D-PHY and C-PHY physical layers underneath them.
Why MIPI exists: the pin and power problem
Consider a 48 MP sensor streaming 30 fps of RAW10 pixels. That is roughly 48M × 10 bits × 30 ≈ 14.4 Gbit/s of payload. A parallel interface at, say, 8 bits would need a clock plus eight data lines toggling slowly, consuming board space and radiating EMI. MIPI instead serializes the stream onto 2–4 differential lanes each running at multiple Gbit/s. The signalling swing on a D-PHY high-speed lane is only about 200 mV around a ~200 mV common mode, so dynamic power stays low even at gigabit rates. Fewer wires, lower swing, less EMI, less cost — that is the entire value proposition.
Rule of thumb: one D-PHY data lane carries one serial bit stream; a shared source-synchronous clock lane times all of them. C-PHY has no separate clock — the clock is embedded in the symbol transitions, so a "trio" of three wires self-clocks.
The layered model
MIPI interfaces are layered much like a networking stack. CSI-2 and DSI define the protocol (packet formats, pixel encodings, virtual channels), while D-PHY/C-PHY define the physical electrical and timing layer. A CSI-2 controller can usually sit on either PHY, which is why you specify them as a pair, e.g. "CSI-2 v3.0 over D-PHY v2.1".
CSI-2: how camera pixels travel
CSI-2 (Camera Serial Interface, 2nd generation) is a unidirectional, packet-based stream from sensor to receiver. Each frame is framed by short packets — Frame Start and Frame End — while the pixel rows ride inside long packets. A long packet header carries a Data Type (e.g. 0x2B for RAW10, 0x1E for YUV422-8), a Virtual Channel ID (so several image streams can be multiplexed on one physical link), and a 16-bit word count, followed by a checksum. This structure is why a single CSI-2 port can carry, say, full-resolution video on VC0 and an embedded statistics/metadata stream on VC1 simultaneously.
A practical detail interview candidates miss: CSI-2 lanes operate in two modes. Low-Power (LP) mode is a slow (~10 Mbit/s), single-ended signalling used for control, line turnaround and entering/leaving sleep; High-Speed (HS) mode is the differential multi-gigabit burst that carries pixels. The transition between them (the LP-to-HS "prepare/zero/trail" sequence) is a classic source of timing bugs when bringing up a new sensor.
DSI: driving the display
DSI (Display Serial Interface) is the mirror image — the SoC sources pixels to the panel. It reuses the same PHY and packet concepts but adds two operating models. In Video Mode, the host streams pixels continuously with real-time timing, like a tiny serialized HDMI; the panel has no framebuffer. In Command Mode, the panel contains its own RAM, and the host writes updates and configuration via DCS (Display Command Set) packets — ideal for always-on and partial-update displays because the link can go idle between writes, saving power. DSI is also bidirectional for reads (panel ID, status), unlike CSI-2.
| Feature | CSI-2 (camera) | DSI (display) |
|---|---|---|
| Direction | Sensor → SoC | SoC → Panel (+reads) |
| Payload | RAW/YUV/RGB pixels, metadata | RGB pixels, DCS commands |
| Modes | Streaming, virtual channels | Video mode / Command mode |
| Typical lanes | 2–4 data + clock | 1–4 data + clock |
D-PHY vs C-PHY: the physical layer
D-PHY is the workhorse. It uses a source-synchronous clocking scheme: a dedicated differential clock lane runs at half the bit rate (double-data-rate), and each data lane samples on both edges. A D-PHY v2.5 lane can hit roughly 4.5 Gbit/s, so four lanes give ~18 Gbit/s. The downside is the extra clock pair.
C-PHY takes a cleverer route. It groups three wires into a "trio" and signals using a multi-level, 3-phase encoding that guarantees a transition every symbol, so the clock is recovered from the data itself — no separate clock lane. Each symbol carries about 2.28 bits, so C-PHY delivers high throughput on fewer wires, which is attractive for high-resolution sensors where routing area is king. The tradeoff is more complex equalization and receiver design.
Numbers that matter: D-PHY throughput ≈ lanes × bit-rate. C-PHY throughput ≈ trios × symbol-rate × 2.28 bits/symbol. A 3-trio C-PHY at 3.5 Gsym/s delivers roughly 24 Gbit/s aggregate.
Where this lands in a real design flow
On the implementation side, the CSI-2/DSI controller and the D-PHY/C-PHY are usually licensed IP — Synopsys DesignWare and Cadence both ship hardened MIPI controller + PHY subsystems that teams integrate rather than build. Verification engineers lean on protocol Verification IP (VIP) from Synopsys or Siemens (Questa) to drive legal and error-injected packet sequences, while the PHY's analog timing (tHS-PREPARE, tCLK-ZERO, skew budgets) is signed off with SPICE and jitter analysis. Getting the LP/HS handshake and lane deskew right in silicon is where most bring-up time goes. If you are designing the SoC side of such a link, firms like Avecas VLSI design services handle exactly this kind of mixed-signal interface integration.
MIPI sits in the same mental box as other serial interfaces you should know — if you understand how USB framing and link states work, DSI's LP/HS state machine will feel familiar, and the differential-pair signalling echoes what you learn studying PCIe lanes and link training.
Want to go from "I know the acronyms" to debugging a real CSI-2 lane deskew failure on a scope? CourseTron's protocol and SoC interface track walks through MIPI, USB and PCIe with hands-on labs — browse the CourseTron courses.
Frequently asked questions
Is MIPI only used in phones?
No. It started in mobile, but CSI-2 and DSI now appear in automotive ADAS cameras, laptops, AR/VR headsets, drones and industrial vision, anywhere a compact camera or display link is needed. Automotive often adds SerDes bridges (GMSL, FPD-Link) to extend CSI-2 over long coax.
When should I choose C-PHY over D-PHY?
Choose C-PHY when you need very high throughput but are pin- or routing-constrained, since it carries more bits per wire with no separate clock lane. Choose D-PHY for simplicity, mature tooling and when the sensor/panel vendor only supports it. Many modern PHYs are "combo" and support both.
What is a virtual channel in CSI-2?
A virtual channel is an identifier in each packet header that lets several independent image streams share one physical link. For example a sensor can send pixel data on VC0 and embedded exposure/statistics data on VC1, and the receiving ISP demultiplexes them.
Why does CSI-2 have both LP and HS modes?
High-speed differential signalling is efficient for bulk pixel transfer but wasteful to keep running when idle. Low-power single-ended mode handles control, idling and mode transitions cheaply, so the link only burns gigabit-rate power during actual image bursts.