In short: USB is a strictly host-driven, polled serial bus where a single host enumerates each attached device, assigns it an address, discovers its endpoints through descriptors, and then schedules four kinds of transfers — control, interrupt, bulk and isochronous — across speeds that climb from 1.5 Mbps Low-Speed to 20 Gbps USB4/USB 3.2 Gen 2x2.
The Universal Serial Bus looks deceptively simple from the outside — plug in, it works — but underneath it is one of the most carefully specified protocols in consumer electronics. For anyone sitting a hardware or verification interview, USB is a favourite topic precisely because it layers physical signalling, packet framing, a stateful enumeration handshake and bandwidth scheduling into one stack. Let us walk through the pieces that actually matter.
One host, many devices: the master–slave model
USB is asymmetric by design. Exactly one host (your PC, phone or SoC) owns the bus and initiates every transaction; devices (also called functions) only ever respond. A device never talks unprompted — even a mouse that "sends" movement is really answering a poll the host issued microseconds earlier. This removes bus arbitration entirely: there are no collisions because only the host schedules traffic. A hub fans out the single host port into many physical ports, but logically it is still one host polling a tree of devices, up to 127 addresses deep.
Because the host drives everything, USB device silicon can be small and cheap: no clock recovery master, no arbitration logic. The host (and its xHCI controller) carries the scheduling burden.
Endpoints and pipes: where data actually flows
Inside a device, data does not flow to "the device" — it flows to an endpoint, a numbered FIFO buffer that is the real source or sink of bytes. Each endpoint has a direction fixed from the host's point of view: IN means device-to-host, OUT means host-to-device. Endpoint 0 is special and bidirectional — it is the mandatory control endpoint every device must implement, used for enumeration. A device can expose up to 15 IN plus 15 OUT additional endpoints.
The logical connection between a host buffer and a device endpoint is a pipe. A webcam, for example, might have EP0 (control), an interrupt IN endpoint for status, and an isochronous IN endpoint streaming video frames — three pipes, three personalities.
Enumeration: how the host learns what you plugged in
When you insert a device, the host has no idea what it is. Enumeration is the choreographed conversation that fixes that, and it runs entirely over endpoint 0:
- Attach & reset — the hub detects the pull-up resistor (on D+ for Full-Speed, D− for Low-Speed) and reports the new device; the host issues a bus reset.
- Default address — the device answers at address 0. The host sends a
GET_DESCRIPTORfor the device descriptor to learnbMaxPacketSize0. - SET_ADDRESS — the host assigns a unique address (1–127); all further traffic uses it.
- Descriptor walk — the host reads the device, configuration, interface and endpoint descriptors, discovering VID/PID, class, and the endpoint map shown above.
- SET_CONFIGURATION — the host picks a configuration; the device is now "configured" and ready for its class driver.
This is why a failed enumeration shows up in a protocol analyser (a Total Phase Beagle, or the USB bus captures you can decode in a logic analyser) as a device stuck re-requesting descriptors at address 0 — a classic debug signature of a bad bMaxPacketSize0 or a crashing firmware descriptor routine.
The four transfer types
USB matches endpoint behaviour to traffic character through four transfer types, each with different guarantees:
| Type | Guarantee | Error handling | Typical use |
|---|---|---|---|
| Control | Guaranteed delivery, reserved bandwidth | Retried, CRC-checked | Enumeration, commands |
| Interrupt | Bounded latency, polled periodically | Retried | Mice, keyboards, HID |
| Bulk | Reliable but no timing promise | Retried | Mass storage, printers |
| Isochronous | Guaranteed bandwidth & timing, no retry | None — dropped on error | Audio, video streams |
The trade-off is the whole point: isochronous audio would rather drop a corrupted packet than stall the stream, while bulk mass-storage would rather retry forever than hand you a corrupt file. Same bus, opposite priorities.
Speeds: from 1.5 Mbps to 20 Gbps
USB's naming is notoriously confusing, so anchor on the raw signalling rates. USB 2.0 defines Low-Speed (1.5 Mbps), Full-Speed (12 Mbps) and High-Speed (480 Mbps) over a half-duplex differential pair (D+/D−) using NRZI with bit-stuffing. USB 3.x adds separate SuperSpeed lanes (two extra differential pairs) running full-duplex with 8b/10b (Gen 1, 5 Gbps) or 128b/132b (Gen 2, 10 Gbps) encoding; USB 3.2 Gen 2×2 bonds two lanes for 20 Gbps, and USB4 tunnels up to 40 Gbps over the Type-C connector.
These high-speed SerDes links are exactly where VLSI design work lives: the PHY, equalisation, and compliance eye diagrams are verified with tools like Synopsys VIP, Cadence Verification IP, and Siemens (Mentor) Questa, and the same signal-integrity discipline carries over to PCI Express link training. If you want the hands-on PHY and protocol-verification track, our team at Avecas design services builds exactly these flows.
Each transaction is itself a mini-sequence of packets: a token packet (host says IN/OUT/SETUP to address+endpoint), an optional data packet, and a handshake (ACK/NAK/STALL). High-Speed slices time into 125 µs microframes; Full-Speed uses 1 ms frames. A device that is not ready answers NAK, and the host simply re-polls later — flow control without a separate mechanism.
Want to go deeper into framing and signalling? See our companion piece on USB signalling and NRZI encoding, or browse the full protocol track on our courses page. For structured VLSI and protocol training programmes, ChipXpert training is the sister brand to check.
Ready to master USB, PCIe and the SerDes PHY flows that interviewers actually ask about? Join the CourseTron Protocols & Interconnects course and build real analyser-driven debugging skills.
Frequently asked questions
Why does USB use a host-driven model instead of letting devices talk freely?
A single scheduling master eliminates bus arbitration and collisions, keeps device silicon cheap, and lets the host guarantee bandwidth for time-critical traffic like isochronous audio. The cost is that devices must wait to be polled.
What is the difference between an endpoint and a pipe?
An endpoint is the physical FIFO buffer inside the device that sources or sinks data. A pipe is the logical association the host creates between one of its buffers and that endpoint. You configure endpoints in firmware; the host opens pipes to them after enumeration.
Why do isochronous transfers never retry on error?
They carry real-time streams such as audio and video where a late packet is useless. Retrying would introduce jitter and stall the stream, so the protocol reserves guaranteed bandwidth but drops any corrupted packet rather than resend it.
Is USB 3.x backward compatible with USB 2.0?
Yes. USB 3.x connectors carry both the legacy D+/D− pair and the new SuperSpeed lanes. A 3.x device in a 2.0 port falls back to High-Speed signalling, and vice versa, which is why the protocol stack must implement both.