In short: I2S is a three-wire synchronous serial bus — a bit clock (BCLK), a word/frame clock (LRCLK or WS) and a data line (SD) — that streams left/right PCM audio samples one bit at a time, with the MSB delayed exactly one BCLK after each LRCLK edge, and it scales up to 8+ channels through its TDM extension.
If you have ever wired a MEMS microphone to a microcontroller, driven a DAC on a dev board, or debugged a crackly audio path on an SoC, you have met I2S (Inter-IC Sound). Introduced by Philips in 1986 and still ubiquitous four decades later, it is the de-facto digital interconnect between audio processors, codecs, DACs and ADCs. This article explains the signal mechanics precisely, the timing gotchas that bite engineers in interviews and on the bench, and how I2S stretches into multi-channel TDM.
The three wires and who drives them
A classic I2S link carries exactly three signals plus ground:
- BCLK (Bit Clock, also SCK) — one pulse per transmitted bit. For stereo it runs at
2 × channels × sample_rate × bits_per_slot. - LRCLK (Left/Right Clock, also WS = Word Select, FS = Frame Sync) — toggles once per sample pair and equals the sample rate exactly. LRCLK low = left channel, LRCLK high = right channel in the standard Philips format.
- SD (Serial Data, also SDATA / DIN / DOUT) — the PCM payload, MSB first.
One device is the controller (formerly "master"), generating BCLK and LRCLK; the other is the peripheral ("slave"), latching or shifting data against those clocks. Direction of SD is independent of who clocks: a microphone peripheral can be the data source while the host still owns the clocks.
Clock math: 48 kHz stereo at 32-bit slots needs BCLK = 2 × 32 × 48 000 = 3.072 MHz, and LRCLK = exactly 48 kHz. Many codecs also want a higher master clock (MCLK), typically 256×fs = 12.288 MHz, to run their internal sigma-delta modulators.
Left/right framing and the one-bit delay
The single most-tested detail of I2S is its framing rule. In the original Philips format the MSB of each word is transmitted one BCLK cycle after the LRCLK transition, not on the same edge. Data is clocked out on the falling edge of BCLK and sampled by the receiver on the rising edge, giving both ends half a bit period of setup/hold margin. This deliberate one-cycle delay is what makes "I2S" different from the "left-justified" and "right-justified" variants that many codecs also support.
Interview trap: "left-justified" format puts the MSB on the same edge as the WS change (no delay); "right-justified" aligns the LSB to the end of the slot. True I2S delays the MSB by one BCLK. Mismatch these and you get a one-sample channel swap or a level that looks bit-shifted — a classic first-boot bug.
Because framing is self-describing — the receiver just watches LRCLK — I2S tolerates slot widths wider than the sample. A 24-bit sample in a 32-bit slot simply pads the trailing BCLKs; the receiver stops caring after the LSB. This is why you configure "data bits" and "slot/frame bits" separately in drivers like the ESP-IDF I2S driver or Linux ALSA SoC (snd_soc_dai) set_fmt/set_tdm_slot calls.
Codecs: where the bits become sound
A codec (coder-decoder) such as the Cirrus/Wolfson WM8960, TI TLV320AIC3x or ESS DACs sits on the far end of the SD line. On playback it feeds the serial stream into an interpolation filter and a sigma-delta modulator, then an analog output stage. On capture it does the reverse. The audio data travels over I2S, but the codec's registers — volume, routing, PLL, sample rate — are configured over a separate control bus, almost always I2C or SPI. Confusing these two buses is another common beginner error: I2S moves samples, I2C/SPI moves settings. If you need a refresher on that control path, see our deep dive on the SPI protocol and the companion I2C protocol guide.
Scaling up: the TDM extension
Plain I2S carries two channels. Modern systems — automotive head units, conferencing speakerphones, multi-mic beamforming arrays — need 4, 8 or 16. The answer is TDM (Time-Division Multiplexing), an upward-compatible evolution. Instead of LRCLK toggling 50/50 per sample, it becomes a short frame-sync pulse that marks the start of a frame containing N equal time slots, and BCLK simply runs fast enough to clock all of them.
| Mode | Channels | Frame sync | BCLK @ 48 kHz, 32-bit slots |
|---|---|---|---|
| Standard I2S | 2 | 50% square (LRCLK) | 3.072 MHz |
| TDM4 | 4 | 1-slot sync pulse | 6.144 MHz |
| TDM8 | 8 | 1-slot sync pulse | 12.288 MHz |
| TDM16 | 16 | 1-slot sync pulse | 24.576 MHz |
Why it matters: TDM8 at 48 kHz already needs a 12.288 MHz bit clock. Edge rates that fast make PCB layout a signal-integrity problem — keep BCLK short, match lengths, and watch reflections. Verification teams model these buses in SystemVerilog and simulate with tools like Synopsys VCS, Cadence Xcelium or Siemens Questa, checking setup/hold against the codec datasheet before silicon ever sees a sample.
TDM slots are typically labelled 0..N-1 and the frame-sync asserts at slot 0. Devices on a shared bus are each assigned a slot (or a pair) and tri-state SD outside their window, letting several ADCs share one data line into the host. Linux's set_tdm_slot(tx_mask, rx_mask, slots, slot_width) is exactly the mechanism that maps a codec to its slot.
Common failure modes on the bench
- Swapped channels: LRCLK polarity inverted — left plays on right. Check WS phase.
- Bit-shifted / quiet audio: format mismatch (I2S vs left-justified) — the one-BCLK delay is wrong.
- Periodic clicks: LRCLK not exactly fs, or MCLK/BCLK not integer-related, causing the codec PLL to slip.
- Noise floor rise: ground bounce or BCLK crosstalk at TDM8/16 rates.
For hands-on labs that build a mic-to-DAC path and scope every edge, teams often pair CourseTron coursework with ChipXpert's VLSI and protocol training, where you verify an I2S/TDM interface in a real RTL testbench.
Ready to master audio and serial interconnects end to end? Explore the protocol modules in our CourseTron course catalog and build a working I2S codec driver from scratch.
Frequently asked questions
Is I2S the same as I2C?
No. Despite the similar name, I2S carries streaming PCM audio samples; I2C is a two-wire bus for configuration and low-rate control. Audio systems commonly use both at once — I2S for sound, I2C for the codec's registers.
Why is the MSB delayed by one bit clock?
The one-BCLK delay decouples the data word from the exact LRCLK edge, giving the receiver clean setup/hold timing and letting any word length fit inside a fixed slot without ambiguity. It is the defining feature of true I2S versus left-justified framing.
How many channels can TDM carry?
Typically 2, 4, 8 or 16 slots per frame, limited by how fast you can run BCLK. At 48 kHz with 32-bit slots, TDM16 already demands a 24.576 MHz bit clock, which pushes PCB signal-integrity limits.
Do I always need an MCLK line?
Not always. Many codecs derive everything from BCLK, but higher-fidelity sigma-delta parts want a separate master clock (often 256×fs) for their internal oversampling. Check the codec datasheet's clocking section.