In short: SPI is a four-wire, full-duplex, master-driven serial bus (MOSI, MISO, SCLK, SS) where one clock master shifts data in and out of one or more slaves simultaneously, with CPOL/CPHA defining the exact clock edge on which bits are sampled and driven.
The Serial Peripheral Interface (SPI) is the workhorse synchronous bus of embedded systems. If you have ever driven a 2.4-inch TFT display, read an ADC, or booted a microcontroller from an external flash, you have almost certainly used SPI running at tens of megahertz. This article unpacks the signalling, the four clock modes that trip up most engineers, and daisy-chaining — the depth you are expected to have in a hardware or firmware interview.
The Four Wires: MOSI, MISO, SCLK, SS
SPI is a single-master, multi-slave bus. The master is the only device that generates the clock and initiates every transfer. There is no addressing in the protocol itself — selection is done with a dedicated chip-select line per slave.
- SCLK — Serial Clock, driven only by the master. Every bit is synchronised to one of its edges.
- MOSI — Master Out, Slave In. The master's transmit line.
- MISO — Master In, Slave Out. The slave's transmit line, held in high-impedance (tri-state) when the slave is not selected.
- SS / CS — Slave Select (active-low, written
SS̄orCS#). Pulling it low enables exactly one slave.
Full-duplex by construction: because MOSI and MISO are separate wires sharing one clock, every clock edge shifts one bit out and one bit in at the same time. Reading a register on an SPI ADC literally means transmitting a dummy byte to clock the result back.
How a Transfer Actually Works
Internally, master and slave each hold an 8-bit (or 16-bit) shift register wired head-to-tail through MOSI and MISO, forming a circular buffer. On each clock period the master shifts its MSB out on MOSI while latching the slave's MSB on MISO. After eight clocks the two registers have completely swapped contents. This is why SPI has no acknowledge, no flow control, and no inherent framing — the number of clock pulses is the protocol. Deassert SS high and the transaction ends.
Clock Modes: CPOL and CPHA
SPI's one real subtlety is timing. Two bits define four modes:
- CPOL (Clock Polarity) — the idle level of SCLK. 0 = idle low; 1 = idle high.
- CPHA (Clock Phase) — which edge samples data. 0 = sample on the leading edge; 1 = sample on the trailing edge.
| Mode | CPOL | CPHA | Data sampled on |
|---|---|---|---|
| 0 | 0 | 0 | Rising edge (leading) |
| 1 | 0 | 1 | Falling edge (trailing) |
| 2 | 1 | 0 | Falling edge (leading) |
| 3 | 1 | 1 | Rising edge (trailing) |
The #1 bring-up bug: master and slave set to different modes. The link appears "almost working" — occasional correct bytes, garbage otherwise — because data is being sampled half a clock period early or late. Always read the slave datasheet's timing diagram and match CPOL/CPHA exactly. Modes 0 and 3 are the most common in practice.
Driving Multiple Slaves
With no addressing, SPI scales to multiple peripherals in two ways:
- Independent (star) selection — MOSI, MISO and SCLK are shared buses; each slave gets its own SS line from a spare GPIO. Simple, but it burns one pin per device.
- Daisy-chaining — the slaves' shift registers are wired in series: master MOSI → slave 1 DIN, slave 1 DOUT → slave 2 DIN, and so on, with a single shared SS and SCLK. The whole chain behaves as one long shift register.
Daisy-Chaining in Depth
Daisy-chaining is common on LED drivers (TI TLC5940), high-channel-count DACs, and addressable strings. To update N devices you clock out N frames back-to-back while SS stays low; the first byte you send ripples to the last device in the chain, and the last byte you send lands in the first device. On the rising SS edge every device latches its register to its outputs simultaneously. The trade-off: one shared select saves pins, but latency grows linearly — refreshing a 32-device chain of 16-bit DACs means clocking 512 bits every frame, so at 20 MHz that is ~26 µs of pure shift time before latch.
Signal integrity matters here. Long shared SCLK traces ring; most designs add a series source-termination resistor and keep the master's drive strength modest. When you validate timing closure on an ASIC or FPGA SPI block, tools like Synopsys PrimeTime or Cadence Tempus check the setup/hold margin of the sampling flop against the clock skew across the chain — the same CPOL/CPHA relationship, now expressed as a static-timing constraint.
SPI vs I²C — When to Choose Which
SPI gives you speed (tens of MHz, even 100+ MHz on QSPI flash) and full duplex, at the cost of pin count and no built-in acknowledgement. I²C trades speed for a two-wire, addressable bus. For the full comparison and the open-drain/ACK mechanics, see our companion guide on the I²C protocol explained, and if you are choosing a bus for a new board, our UART vs SPI vs I²C selection guide lays out the decision matrix. For hands-on labs on all three, explore the CourseTron embedded course catalogue. Teams building production silicon that embeds these interfaces often bring in a design partner such as Avecas VLSI design services for RTL-to-GDSII sign-off.
Ready to go from "it almost works" to protocol fluency? The CourseTron Embedded Protocols course walks you through building and debugging SPI, I²C and UART links on real hardware with a logic analyzer.
Frequently Asked Questions
Why does reading an SPI device require sending data?
SPI is full-duplex and clocked only by the master. The slave can only put bits on MISO while SCLK is toggling, and SCLK only toggles while the master shifts something out on MOSI. So to read N bytes you transmit N dummy bytes to generate the clocks.
What is the difference between CPOL and CPHA?
CPOL sets the clock's idle level (low or high); CPHA selects whether data is sampled on the leading or trailing clock edge. Their four combinations are SPI modes 0–3, and both the master and slave must agree on the same mode.
How many devices can share one SPI bus?
In star topology you are limited mainly by available chip-select GPIOs and bus capacitance. In a daisy chain you can connect many devices with a single SS, bounded by acceptable shift latency and signal integrity on the shared clock.
Is SPI faster than I²C?
Generally yes. SPI commonly runs at 10–50 MHz and QSPI flash well beyond 100 MHz, while standard I²C tops out at 400 kHz (1 MHz in Fast-mode Plus). SPI also has lower per-bit overhead because it lacks addressing and acknowledge phases.