In short: I2C is a two-wire, multi-device serial bus where an addressed master clocks data to and from slaves using open-drain SDA/SCL lines, framing every transfer with START/STOP conditions, 7- or 10-bit addressing, and per-byte ACK/NACK handshaking — with clock stretching and arbitration letting slow peripherals and multiple masters share the same pair of wires.
Inter-Integrated Circuit (I2C), invented by Philips (now NXP) in 1982, is the workhorse bus that glues together the "slow and nearby" parts of almost every embedded system: EEPROMs, temperature sensors, RTCs, IMUs, power-management ICs and HDMI DDC channels. Its appeal is economy — just two wires, SDA (serial data) and SCL (serial clock), shared by up to 127 devices. This article walks through the mechanics that make that sharing work, and why each rule exists.
Why open-drain? The electrical foundation
Both SDA and SCL are open-drain (or open-collector): a device can only pull the line low; it never actively drives it high. External pull-up resistors (typically 2.2 kΩ–10 kΩ to VDD) restore the idle-high state. This is not an accident — it is what makes the whole protocol safe. Because no device ever fights another by driving opposite logic levels, you can wire-AND many devices together without bus contention or blown drivers. It also enables two defining features: a slave can hold SCL low (clock stretching) and two masters can detect collisions during arbitration.
Bus capacitance matters. The I2C spec caps total bus capacitance at 400 pF. The pull-up value and Cbus set the rise time (τ ≈ R×C). At 400 kHz Fast-mode a 10 kΩ pull-up into 400 pF gives a ~4 µs rise time — far too slow. This is why long or crowded I2C buses misbehave; you drop the resistor to ~1.5–2.2 kΩ or add an active bus accelerator.
START and STOP: framing a transaction
The bus is quiet when both lines are high. The master signals the start and end of a transfer by violating the normal data rule (data only changes while SCL is low):
- START (S): SDA falls from high to low while SCL is high.
- STOP (P): SDA rises from low to high while SCL is high.
- Repeated START (Sr): a new START issued without an intervening STOP — used to change direction (e.g. write a register address, then read it back) without releasing the bus to other masters.
Addressing and the R/W bit
Immediately after START, the master sends the first byte: a 7-bit address plus one R/W bit (0 = write, 1 = read). All slaves compare the address against their own; the one that matches responds, the rest ignore the rest of the transaction. With 7 bits you get 112 usable addresses (16 are reserved, including 0x00 for general-call and the 0b1111xxx block for 10-bit addressing). When 112 is not enough, 10-bit addressing uses a two-byte scheme that keeps backward compatibility. Address collisions between two identical sensors are a classic field bug — solved with address-select pins, an I2C mux (e.g. TCA9548A), or separate buses.
ACK / NACK: the per-byte handshake
I2C validates every single byte. After the transmitter clocks out 8 bits, it releases SDA for a 9th clock. The receiver pulls SDA low to ACK ("got it, send more") or leaves it high for a NACK. A NACK is meaningful, not just an error:
- After the address byte, a NACK means no slave matched that address — the standard way probing tools like
i2cdetectmap a bus. - During a master read, the master deliberately NACKs the final byte to tell the slave "stop sending," then issues STOP.
Clock stretching: letting slow slaves breathe
Because SCL is open-drain, a slave that needs more time — an ADC still converting, an MCU-based slave whose firmware hasn't filled the buffer — can hold SCL low after the master releases it. The master, seeing SCL still low, waits. This is clock stretching, and it is the one place a slave controls timing. It is powerful but a frequent source of grief: many hardware I2C masters (famously some Raspberry Pi SoCs and older STM32 peripherals) have buggy or missing stretch support, so sensors like certain SHT3x parts misbehave. Always check whether both ends honour stretching, and bound it with a timeout so a stuck slave doesn't hang the bus forever.
Multi-master arbitration
I2C permits several masters on one bus. If two start transmitting at once, arbitration resolves it bit-by-bit, non-destructively, thanks again to open-drain: each master reads back the line while driving it. A master writing a 1 (releasing SDA high) that sees the line pulled low by another master knows it lost arbitration — it stops immediately, and because the winner was driving low anyway, its data is uncorrupted. The lower address / data value wins. Combined with clock synchronization (masters AND their SCL low periods together), this lets independent controllers coexist without a central arbiter.
Speed modes and how I2C compares
| Mode | Max clock | Typical use |
|---|---|---|
| Standard | 100 kHz | EEPROMs, RTCs, legacy sensors |
| Fast-mode | 400 kHz | Most modern sensors / PMICs |
| Fast-mode Plus | 1 MHz | Higher-throughput sensors |
| High-speed | 3.4 MHz | Displays, large EEPROM reads |
If you need higher throughput or full-duplex transfers, a push-pull bus like SPI is usually the better fit — our companion piece, SPI protocol explained, covers that trade-off, and UART vs SPI vs I2C helps you choose between the three for a given design. When you prototype, a logic analyzer plus protocol decoder (Saleae, or the I2C trigger/decode on a Siemens/Keysight scope) will save hours; for digital-design coursework these same waveforms map directly onto RTL you can simulate in Synopsys VCS or Cadence Xcelium.
Reserved address trap. Address 0x00 is the general-call address and 0x7F-adjacent blocks are reserved. A real-world bring-up bug is a slave strapped to a reserved address that silently never ACKs — always cross-check the datasheet's address table before blaming your firmware.
If you are building silicon or board-level peripherals that speak I2C and want design-house support, our sister team at Avecas VLSI design services implements and verifies these interfaces as part of SoC bring-up.
Want to move from reading waveforms to writing and verifying bus controllers? The CourseTron Embedded Protocols course builds I2C, SPI and UART masters/slaves from the ground up, with hardware labs and RTL assignments. Browse the curriculum →
Frequently asked questions
Why does I2C use open-drain instead of push-pull?
Open-drain lets many devices share one wire safely: a device can only pull low, so there is never a driver fight. It is what enables clock stretching and non-destructive multi-master arbitration — neither of which a push-pull bus can do on a shared line.
What is the difference between a NACK and a bus error?
A NACK is a valid protocol signal — SDA staying high on the 9th clock. It can mean "no device at this address" or "stop sending (end of read)." A bus error (e.g. SDA stuck low) is an electrical fault, usually a hung slave, cleared by toggling SCL up to 9 times or asserting a bus-reset.
How many devices can I put on one I2C bus?
Logically up to 112 with 7-bit addressing (127 minus reserved), but practically you are limited by the 400 pF capacitance ceiling. Identical devices also clash on address, so you use address-select pins or an I2C mux rather than the full address space.
Why does clock stretching cause so many bugs?
Because some hardware I2C masters implement it incompletely. If the master doesn't wait while a slave holds SCL low, it reads garbage. Check both datasheets, enable stretching in the driver, and always set a timeout so a stuck slave can't freeze the bus.