In short: A PCB goes from schematic capture to fabrication output through a disciplined chain — netlist generation, component placement, layer stackup, constraint-driven routing, DRC/DFM verification, and Gerber/ODB++ export — where each stage feeds verified intent to the next and a single unchecked escape can scrap an entire panel.
Every physical electronic product you have ever touched started as a few connected symbols on a schematic sheet and ended as a stack of copper, resin and solder mask that a fab could actually build. The PCB design flow is the engineering bridge between those two worlds. Unlike a software build, you cannot hot-patch a board after the panel is etched — so the flow is built around catching errors early and freezing intent before it becomes expensive copper. Below we walk the end-to-end flow the way a working hardware engineer runs it in tools like Cadence Allegro, Siemens Xpedition, Altium Designer or KiCad.
1. Schematic Capture and the Netlist
The flow begins with schematic capture: you draw the logical design — op-amps, an STM32, decoupling caps, connectors — and wire their pins together. This is purely connectivity and intent; there is no geometry yet. When the schematic is complete, the tool compiles it into a netlist, a machine-readable list of every electrical node (a "net") and the component pins that share it. A typical mid-complexity IoT board might carry 300–600 nets and 150 components. The netlist is the contract that governs everything downstream: if two pins are not on the same net here, no amount of routing will connect them later.
Key fact: The netlist — not the routed copper — is the single source of truth. Layout-versus-schematic (LVS) checks and DRC both validate the board against this netlist, which is why a sloppy schematic silently corrupts every later stage.
2. Footprint Assignment and Component Placement
Before geometry exists, every schematic symbol must be mapped to a physical footprint — the exact copper pads, courtyard and 3D body that match the real part's datasheet (e.g. a 0402 resistor vs. a QFN-48 with a thermal pad). Placement is then the single highest-leverage manual decision in the flow. Good placement makes routing almost trivial; bad placement makes it impossible. Engineers place by function: tight loops for switching regulators, decoupling caps within a few millimetres of their IC power pins, crystals hugging the MCU, and connectors on the board edge. A 10 mm detour on a 100 MHz trace adds roughly 70 ps of delay — enough to blow a timing budget on DDR memory.
3. Layer Stackup Definition
In parallel you define the stackup: how many copper layers, their thickness, and the dielectric between them. This is not cosmetic — it sets the characteristic impedance of every controlled trace. A common 4-layer stackup is Signal / Ground / Power / Signal, which gives high-speed signals a tight return path on an adjacent plane. The table below shows how trace width and spacing scale with impedance targets.
| Interface | Target impedance | Typical geometry (4-layer) |
|---|---|---|
| Single-ended (e.g. SPI) | 50 Ω | ~0.18 mm trace, ref plane 0.2 mm below |
| USB 2.0 differential | 90 Ω | 0.15 mm trace / 0.15 mm gap |
| Ethernet / MIPI | 100 Ω | 0.13 mm trace / 0.18 mm gap |
4. Constraint-Driven Routing
Routing physically draws the copper for each net. Modern flows are constraint-driven: before you route a single trace, you enter rules — minimum trace/space, differential-pair gaps, length-matching tolerances, via styles — into a constraint manager. The router (interactive or auto, as in Allegro's or Xpedition's engines) then enforces them live, so you cannot accidentally violate a 100 Ω pair's 5 mil matching window on a DDR bus. High-speed buses get length-tuned with serpentine/accordion segments so all bits arrive within picoseconds of each other.
5. DRC: Design Rule Checking
With copper placed, DRC runs the layout against the manufacturer's capability rules and your electrical constraints: minimum annular ring, copper-to-copper spacing, acid traps, sliver polygons, unconnected nets, and silkscreen over pad. A clean DRC does not mean the board works — it means the board is buildable and matches the netlist. This is also where LVS confirms the routed copper still equals the original schematic intent. Treat every waived violation as a conscious risk, documented, not clicked away.
Key fact: Fabs publish a capability sheet (e.g. 4/4 mil trace/space, 0.2 mm min drill). Importing those limits as DRC rules before routing — not after — is the difference between a first-pass board and a two-week respin.
6. DFM and Fabrication Output
DRC proves correctness; DFM (design for manufacturing) proves yield. DFM analysis flags features that are legal but risky: tombstone-prone pad asymmetry, insufficient solder-mask dam, panelization problems. Once DFM passes, you generate the fabrication package — historically Gerber RS-274X plus an Excellon drill file, increasingly the richer, single-file ODB++ or IPC-2581 formats that carry netlist and stackup data the fab can verify independently. A pick-and-place (centroid) file and BOM complete the handoff. This is the frozen artifact the fab etches; see our deeper guide on PCB design for manufacturing and the companion piece on stackup and impedance control for how to tune these outputs for yield.
Teams that build silicon as well as boards often run this flow alongside chip-level physical design; if you want to see how the same place-and-route discipline scales down to transistors, the design-services engineers at Avecas VLSI design services run both worlds daily.
Want to run this flow end-to-end on a real board — schematic to Gerbers — with feedback from working engineers? Explore the hands-on PCB track in the CourseTron course catalogue.
Frequently Asked Questions
What is the difference between DRC and DFM?
DRC checks that your board obeys electrical and manufacturability rules and still matches the netlist — it answers "is this buildable and correct?". DFM is a yield-oriented analysis that flags legal-but-risky features (tombstoning, thin mask dams) that would lower assembly yield even though they pass DRC.
Why is component placement considered the most important step?
Placement fixes the physical relationships every later stage must respect. Good placement shortens high-speed traces, keeps return paths tight and makes routing almost automatic; poor placement forces long detours that add delay and noise, and can make a design unroutable regardless of router skill.
What file formats does a fab actually need?
Classically Gerber RS-274X for each copper/mask/silk layer plus an Excellon drill file, a centroid (pick-and-place) file and a BOM. Modern flows increasingly ship ODB++ or IPC-2581, which bundle copper, drill, stackup and netlist into one verifiable package.
Can you skip the netlist and route directly?
No. The netlist is the contract that DRC and LVS validate against. Without it there is no way for the tool to tell a correct connection from a short, so every automated check downstream loses its reference and errors escape to fabrication.