Verilog Half Adder and DEMUX

In short: A half adder is one XOR plus one AND (sum = a ^ b, carry = a & b), a 1-to-4 demultiplexer routes one input to one of four outputs using two select bits, and the demux is simply a 2-to-4 decoder whose enable pin carries the data.

Half adders and demultiplexers are the first two circuits most Verilog courses assign, and the first two that interviewers use to check whether you think in hardware or in software. The adder tests whether you know which gates a plus sign becomes. The demux tests whether you see that a decoder and a demultiplexer are the same netlist wearing different labels. Let us build both, then connect them.

The half adder: two gates, two outputs

A half adder adds two single bits. The result needs two bits because 1 + 1 = 10 in binary: a sum bit and a carry bit. Sum is high when exactly one input is high, which is XOR. Carry is high only when both are high, which is AND. If you want the arithmetic background first, see our notes on the half adder and how it compares in half adder and full adder.

Writing it in Verilog three ways

The same function can be described structurally, with continuous assignments, or behaviorally. All three synthesize to identical logic in Synopsys Design Compiler or Cadence Genus; the difference is readability and how much typing you risk.

// dataflow
module half_adder(input a, b, output sum, carry);
  assign sum   = a ^ b;
  assign carry = a & b;
endmodule

// behavioral: one line using the 2-bit result
module half_adder_b(input a, b, output reg sum, carry);
  always @(*) {carry, sum} = a + b;
endmodule

Key fact: in {carry, sum} = a + b the left side is 2 bits wide, so Verilog evaluates the addition at 2 bits and the carry is not lost. Write sum = a + b into a 1-bit target and the carry silently vanishes. Widths in expressions follow the context, a rule that also drives sign extension in Verilog.

In the behavioral version, outputs are declared reg only because they are assigned inside an always block; no flip-flop is created. That distinction is explained in reg vs wire in Verilog. Because the block is combinational, use blocking assignments, as covered in blocking vs non blocking Verilog.

The 1-to-4 demultiplexer

A multiplexer selects one of many inputs; a demultiplexer does the reverse. The 1-to-4 demux takes one data input d and two select lines s1 s0, and drives d onto exactly one of four outputs while the other three stay at 0. If you have studied the 4 to 1 multiplexer, picture it mirrored.

module demux_1to4(input d, input [1:0] s, output reg [3:0] y);
  always @(*) begin
    y = 4'b0000;          // default prevents latches
    y[s] = d;             // route d to the selected line
  end
endmodule

Key fact: the default assignment y = 4'b0000 before the indexed write is what keeps the block a pure combinational circuit. Omit it and synthesis tools infer latches for the unselected bits, and lint tools such as Synopsys SpyGlass or Siemens Questa Lint will flag it.

Demux and decoder are the same circuit

Each output of the demux equals d & (s == i). A 2-to-4 decoder with an enable input en computes y[i] = en & (s == i). Replace en with d and the equations are identical. That is why a decoder with enable is sold as a demux in catalogue parts such as the 74HC138 (3-to-8) and why a 3-to-8 decoder gives you a 1-to-8 demux for free.

Watch the routing in motion

The animation below holds d = 1 while the select value counts 00, 01, 10, 11. Exactly one output lights up at a time.

Structural version and verification

To practise structural modeling in Verilog, build the demux from AND gates fed by an inverted-select decoder: y0 = d & ~s1 & ~s0, y1 = d & ~s1 & s0, and so on. That costs four 3-input ANDs and two inverters, roughly ten gate equivalents. A 4-bit ripple chain of half adders is not possible, though, since the second bit onward must accept a carry-in, which is where the full adder takes over.

For simulation, give every testbench a `timescale (see timescale directive in Verilog) and loop exhaustively: the half adder has 4 input combinations, the demux 8. Exhaustive checking is cheap at this size and catches every bug. Run it in Siemens Questa, Synopsys VCS, Cadence Xcelium or the free Icarus Verilog, then synthesize in Vivado to confirm the half adder maps to a single LUT2 pair and the demux to four LUT3s.

Interview traps worth rehearsing

• Latch inference: missing the default in the demux always block.
• Width loss: assigning a + b to a 1-bit sum.
• Sensitivity list: use @(*) or always_comb, never a hand-written partial list.
• Universal gates: a half adder needs five NAND gates, a favourite follow-up question.

Key fact: the half adder has no carry-in, so it cannot be chained. Two half adders plus an OR gate make a full adder, which is the usual next question.

If you want guided practice on these building blocks, with simulation labs and tool flows, explore our CourseTron courses. For instructor-led placement training in India see ChipXpert.

Ready to go from gates to FPGA projects? Join the Verilog and FPGA track on CourseTron and build, simulate and synthesize every circuit in this article.

FAQ

Why is a half adder called "half"?

It adds two bits but has no carry-in, so it handles only half of what a multi-bit adder stage must do. A full adder adds a third input, the carry from the previous stage.

Is a demultiplexer the same as a decoder?

Functionally yes, when the decoder has an enable pin. Feed data into enable and the decoder behaves as a demux. Without an enable, a decoder cannot carry data.

Why do outputs of a demux that are not selected stay at 0?

Each output is an AND of the data bit and a select-match term. When the select does not match, that AND is 0 regardless of the data.

Does a half adder in Verilog create flip-flops?

No. Using reg for outputs inside an always @(*) block still infers purely combinational logic.