Half Adder AND Full Adder

In short: A half adder adds two bits (Sum = A⊕B, Carry = A·B) but cannot accept a carry-in, while a full adder adds three bits (A, B, Cin) and is built from two half adders plus an OR gate, which is what makes multi-bit addition possible.

Why interviewers keep asking this

Every ALU, address generator, MAC unit and CRC-adjacent datapath you will ever synthesize reduces to adders. The half adder and full adder are the smallest examples where you must connect a truth table to a Boolean expression and then to real gates. A good answer does not stop at the table: it derives the equations, counts gates, and talks about delay. That is what we do below, with the follow-up questions interviewers actually use.

The half adder: two inputs, no carry-in

A half adder adds two single bits and produces a Sum and a Carry. Adding 1 + 1 gives binary 10, so Sum = 0 and Carry = 1.

Reading the columns: Sum is high when exactly one input is high, so Sum = A ⊕ B. Carry is high only when both are high, so Carry = A · B. The circuit is one XOR and one AND sharing the same inputs. It is "half" because it has no input for a carry coming from a lower bit position, so it only suits the least significant bit, or a place where no carry can arrive.

Key fact: a half adder needs just 2 gates (1 XOR + 1 AND). Its sum output is exactly the XOR parity of the inputs.

The full adder: three inputs, the real building block

To add multi-bit numbers, each stage must also add the carry from the stage below. A full adder takes A, B and Cin and returns Sum and Cout. The result is a 2-bit number between 0 and 3, which fits neatly into Sum (LSB) and Cout (MSB).

Sum is 1 whenever an odd number of inputs are 1, so Sum = A ⊕ B ⊕ Cin. Cout is the majority function: it is 1 when at least two inputs are 1, giving Cout = AB + BCin + ACin. Factoring with P = A⊕B gives the form used in practice: Cout = AB + Cin·(A⊕B). The two forms are equal, and being able to prove that on a whiteboard is a classic interview moment.

Key fact: Sum is a 3-input parity function and Cout is a 3-input majority function. Mention both words and you sound fluent.

Building a full adder from two half adders

The factored form maps directly onto hardware. The first half adder computes P = A⊕B and G = A·B. The second half adder adds P and Cin, producing Sum = P⊕Cin and a partial carry P·Cin. An OR gate merges the two carry sources: Cout = G + P·Cin. Total: 2 XOR, 2 AND, 1 OR, which is 5 gates. The names P and G (propagate and generate) are not accidental; the same signals drive carry-lookahead adders later.

Half adder vs full adder at a glance

The same primitives appear in subtraction: swap the roles and you get the half subtractor, covered in our half subtractor guide. Once you have a chain of full adders, delay becomes the next topic, which we explore in ripple carry adders.

Chaining full adders: the carry ripple

Connect Cout of stage i to Cin of stage i+1 and you have a ripple-carry adder. The animation below shows a carry bit travelling stage by stage. The worst case is when the carry starts at bit 0 and flips every stage, as in 0111...1 + 1. With about two gate delays per Cout (AND then OR), a 32-bit ripple adder has a critical path near 64 gate delays, versus roughly 2 log2(32) levels for a lookahead structure.

Key fact: ripple-carry delay is O(n). That is why high-speed ALUs use carry-lookahead or prefix adders built from the same P and G signals.

RTL, synthesis and silicon reality

In Verilog you rarely instantiate gates. You write the behaviour and let synthesis choose the structure:

module full_adder(input a, b, cin, output sum, cout);
  assign {cout, sum} = a + b + cin;
endmodule

Tools such as Synopsys Design Compiler, Cadence Genus and Siemens Precision map this to library cells; most standard-cell libraries even include dedicated full-adder and half-adder cells (often named FA and HA), which are cheaper than five discrete gates. In CMOS, the classic "mirror adder" implements a full adder in 28 transistors, with Cout computed first and reused to generate Sum. For FPGAs, the carry chain is a hard wire in the slice, so Xilinx and Intel devices ripple faster than a LUT-built chain would. If your team needs adder and datapath design done properly, Avecas design services works on exactly this kind of RTL-to-GDS problem.

Common interview traps

• Writing Cout = A·B + Cin and forgetting the XOR term. Test it with A=0, B=0, Cin=1: Cout must be 0.
• Claiming the OR gate in the full adder could be an XOR. It can, because G and P·Cin are never both 1, but explain why before saying so.
• Building everything from NAND: a half adder takes 5 two-input NAND gates, and a full adder takes 9.
• Confusing Cin-to-Sum delay (one XOR) with A-to-Cout delay (XOR, AND, OR).

Practice these on paper, then simulate them. Our ChipXpert VLSI training program runs these exact whiteboard drills, and the CourseTron courses let you verify them in a simulator.

Ready to go from adders to full ALU design? Explore the Digital Electronics track in the CourseTron courses and build, simulate and synthesize your first datapath this week.

Frequently asked questions

Why is it called a half adder?

It handles only half of what an adder needs: it adds two bits but has no input for the carry coming from the previous bit position.

Can a full adder be made from half adders?

Yes. Two half adders plus one OR gate form a full adder, with the OR combining the two partial carries.

How many gates does a full adder need?

Five basic gates (2 XOR, 2 AND, 1 OR), or 9 two-input NAND gates, or 28 transistors in a mirror-adder CMOS cell.

Why is a ripple-carry adder slow?

Each stage's carry-out depends on the previous stage, so delay grows linearly with the number of bits.