Half Subtractor

In short: A half subtractor subtracts one bit from another using an XOR gate for the difference (D = A ⊕ B) and an AND gate with an inverted A for the borrow (Bout = A′·B), making it a half adder with a single inverter added to the carry path.

What a half subtractor actually does

Subtraction in binary is the mirror image of addition. When you compute A − B for two single bits, there are only four cases, and exactly one of them cannot be done without help: 0 − 1. A single bit cannot go below zero, so the circuit "borrows" from the next more significant position. In decimal terms, borrowing 1 from the neighbour adds 2 to the current position, so 0 − 1 becomes (2 + 0) − 1 = 1, with a borrow flag raised to tell the next stage that it owes one unit.

A half subtractor is the smallest circuit that captures this. It has two inputs, the minuend A and the subtrahend B, and two outputs: the difference D and the borrow-out Bout. It is called "half" because it has no borrow-in. It can therefore handle only the least significant bit of a multi-bit subtraction. Anything wider needs the full subtractor, which adds a third input to absorb the borrow from the previous stage.

Truth table and the two equations

Work through the cases by hand first. Always read the order as A minus B, not B minus A, because subtraction is not commutative.

Read the D column: it is 1 whenever the inputs differ, which is the definition of XOR. So D = A ⊕ B = A′B + AB′. Read the Bout column: it is 1 in exactly one row, where A = 0 and B = 1. That is a single minterm, so Bout = A′·B. No Karnaugh map is needed; the function is already minimal in sum-of-products form.

Key fact: the difference output is identical for A − B and B − A. Only the borrow output is asymmetric, which is why swapping the operands of a half subtractor changes Bout but not D.

The gate-level circuit

The implementation needs three gates: one XOR, one NOT and one AND. The NOT gate sits on input A and feeds the AND gate; B goes directly to both the XOR and the AND. Figure 1 shows the wiring.

The relationship to the half adder

Compare the equations. A half adder gives Sum = A ⊕ B and Carry = A·B. The half subtractor gives D = A ⊕ B and Bout = A′·B. The XOR is shared, and the only structural change is that one input of the AND is inverted. This is a favourite interview observation: "How do you turn a half adder into a half subtractor?" Answer: put an inverter on A before the carry AND gate, and rename carry to borrow.

Key fact: in a half adder the second output is 1 for one input row (A=B=1). In a half subtractor it is also 1 for one input row (A=0, B=1). Both are single-minterm functions, so each costs exactly one two-input gate.

Watching it work

The animation below cycles through the four input combinations once per second. Follow the highlighted row and watch the difference and borrow values update on the right.

Variants, cost and what synthesis does with it

You can build the half subtractor in several ways. The classic form uses XOR, NOT and AND (three gates). A NAND-only version needs five two-input NAND gates, the same count as a NAND-only half adder, because the shared structure NAND(A,B) can be reused: D = NAND(NAND(A, N), NAND(B, N)) where N = NAND(A,B), and the borrow follows from NAND(N, B) inverted appropriately. In a standard-cell library, the inverted-input AND is often available as a single cell (for example an AND2 with one inverted input, sometimes called an "AND2B" cell), so the inverter disappears into the cell.

In practice you rarely instantiate these gates by hand. In Verilog you write assign {bout, d} = {~a & b, a ^ b}; or simply let a behavioural subtractor infer the logic. Synopsys Design Compiler, Cadence Genus and Siemens Precision all map such expressions onto the library's XOR and AND-with-inverted-input cells. A tool will also notice that a half subtractor and a half adder share the XOR term and may merge them when both exist in the same datapath, a small example of logic sharing.

module half_sub (input a, b, output d, bout);
  assign d    = a ^ b;
  assign bout = ~a & b;
endmodule

Timing is trivial: both outputs have a critical path of one gate level for bout and one XOR delay for d. If your library XOR is 80 ps and AND2 is 50 ps at a typical corner, D settles after roughly 80 ps and Bout after roughly 50 ps plus the inverter. The inverter delay on A is the reason the borrow path is slightly slower than a half adder's carry path, unless the library has an inverted-input cell.

Key fact: a half subtractor is almost never used on its own in real datapaths. Hardware subtracts using two's complement (invert B, add 1 with carry-in = 1) on a single adder, so the full subtractor and half subtractor matter mainly for teaching, for understanding borrow chains, and for interview questions.

Common interview traps

• Which input is inverted? It is the minuend A, not B. Inverting B gives A·B′, which is the borrow of B − A.
• Cascading half subtractors. Two half subtractors plus an OR gate build a full subtractor: the first computes A − B, the second subtracts the incoming borrow from that result, and the OR combines the two borrow outputs. This is explained in the full subtractor article.
• Counting minterms. D has two minterms (m1, m2); Bout has one (m1). Knowing this lets you write the Karnaugh maps without drawing them.
• Relation to comparators. The borrow output is exactly the "A < B" flag for single bits, which is how a magnitude comparator grows from the same primitives.

If you want to practise writing and synthesising this kind of logic with real EDA flows, the design engineers at Avecas use the same fundamentals when reviewing arithmetic datapaths, and the hands-on programmes at ChipXpert VLSI training turn these gates into working RTL and layout.

Ready to go beyond single-bit gates? Explore the full digital design track on the CourseTron courses page and build adders, subtractors and ALUs step by step.

Frequently asked questions

What is the difference between a half adder and a half subtractor?

Both use an XOR for the first output. The half adder's second output is A·B (carry); the half subtractor's is A′·B (borrow). The inverter on A is the only logical difference.

Why is it called a "half" subtractor?

It has no borrow input, so it cannot accept a borrow from a lower bit. It is therefore only suitable for the least significant bit; a full subtractor handles all higher positions.

What are the Boolean expressions for a half subtractor?

Difference D = A ⊕ B = A′B + AB′, and Borrow Bout = A′·B.

Can a half subtractor be built with only NAND gates?

Yes. NAND is universal, so five two-input NAND gates (with a shared intermediate term) are enough to realise both D and Bout.