In short: A 4-to-1 multiplexer routes one of four data inputs to a single output using two select lines, implemented as Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3, or equivalently as a tree of three 2-to-1 muxes.
What a 4-to-1 mux actually does
A multiplexer is a digital switch controlled by data. The 4-to-1 version has four data inputs (I0 to I3), two select inputs (S1, S0) and one output Y. The select pair is read as a binary number, and the input with that index is passed through. With n select lines you can address 2n inputs, which is why two lines suffice for four inputs.
Key fact: a mux is a combinational circuit. Y depends only on the present inputs, with no memory and no clock. Only propagation delay separates a select change from the output change.
Muxes are everywhere in real silicon: register-file read ports, ALU result selection, scan-mux flops in DFT, clock selection (with care), and as the building block inside FPGA look-up tables. If you understand the 4-to-1 well, the 8-to-1 and 16-to-1 follow naturally; see our 8-to-1 multiplexer guide for the scale-up.
Truth table and Boolean expression
A full truth table has six inputs and 64 rows, which is wasteful. The compact (function) table lists only the select combinations and states which input appears at Y.
| S1 | S0 | Y |
|---|---|---|
| 0 | 0 | I0 |
| 0 | 1 | I1 |
| 1 | 0 | I2 |
| 1 | 1 | I3 |
Reading each row as a minterm of the select lines gives the sum-of-products form:
Y = S1'·S0'·I0 + S1'·S0·I1 + S1·S0'·I2 + S1·S0·I3Each product term is a decoder output ANDed with one data input. The four select minterms are mutually exclusive, so exactly one term can be active at a time, and the OR collects it. This is the "decoder plus AND-OR" view of a mux, and it is the one interviewers expect you to draw first.
Gate-level logic diagram
Counting cost: four 3-input ANDs, one 4-input OR and two inverters. In a 2-input-gate library that is roughly 3 gates per AND-of-three, giving about 12 NAND2-equivalents for ANDs plus 3 for the OR, so on the order of 17 to 20 gates. Synthesis tools such as Synopsys Design Compiler or Cadence Genus will not keep this structure anyway; they map to AOI22/AOI222-style cells or dedicated MUX2/MUX4 library cells chosen for area and delay.
Building it as a tree of 2-to-1 muxes
A 2-to-1 mux implements Y = S'·A + S·B. Three of them make a 4-to-1: the first rank, driven by S0, picks between I0/I1 and I2/I3; the second rank, driven by S1, picks between those two results.
Key fact: an N-to-1 mux needs N-1 two-to-one muxes in a tree and log2N levels of delay. For N = 4 that is 3 muxes and 2 levels; for N = 8 it is 7 and 3.
The tree is not just a teaching trick. In CMOS, a 2-to-1 mux built from two transmission gates costs 4 transistors plus an inverter for the select (6 total). A tree therefore costs about 18 transistors for the 4-to-1, while a one-hot pass-gate version with a decoded select needs only 8 pass transistors, at the price of a decoder. Pass-gate trees also degrade signal edges across stages, so designers insert a buffer every two or three levels.
Seeing it work
The animation below cycles the select value through 00, 01, 10 and 11 and highlights the path that is open at each step.
Implementation in HDL and what the tools do with it
In Verilog a behavioural description is a single line, and synthesis decides the structure:
module mux4 (input [3:0] i, input [1:0] s, output y);
assign y = i[s];
endmoduleA case statement or the conditional operator gives the same result. The classic bug is an incomplete case inside an always block without a default: the tool infers a latch, which is sequential logic you did not intend. Lint tools (Synopsys SpyGlass, Siemens Questa Lint) flag it, and so does Design Compiler. In FPGAs (Xilinx/AMD, Intel) a 4-to-1 mux with six inputs total fits exactly in one 6-input LUT, which is why FPGA designers rarely think about gates at all.
Timing-wise, the select-to-output path is usually critical because select signals often fan out to many muxes (a 32-bit bus mux loads each select 32 times). Buffer trees or duplicating the decoder fix this. If you want to practise this on real flows, the team at Avecas VLSI design services builds exactly these datapaths at scale.
Beyond data selection: mux as a universal gate
A 4-to-1 mux can implement any 2-variable function by wiring A and B to the selects and tying the data inputs to the truth-table column. For XOR, tie I0 = 0, I1 = 1, I2 = 1, I3 = 0. Likewise a 4-to-1 implements any 3-variable function if one variable is fed into the data inputs as 0, 1, C or C' (the Shannon-expansion trick), a favourite exam question. Cascading to 8-to-1 and beyond follows the same logic; continue with the 8-to-1 mux, then explore the inverse operation in demultiplexers and decoders. For hands-on, instructor-led RTL and verification training, see ChipXpert VLSI training.
Key fact: any n-variable function can be built from a 2(n-1)-to-1 mux, with the last variable (or its complement, 0 or 1) on the data inputs.
Want to go from theory to silicon-ready design? Explore the Digital Electronics track in our CourseTron courses with guided labs and interview practice.
Frequently asked questions
How many select lines does a 4-to-1 multiplexer need?
Two. The select lines encode a binary index into four inputs, since 22 = 4.
How many 2-to-1 muxes make a 4-to-1 mux?
Three: two in the first rank driven by S0 and one in the second rank driven by S1.
What is the Boolean expression of a 4-to-1 mux?
Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3.
Can a mux implement logic functions?
Yes. A 4-to-1 mux implements any 2-variable function directly and any 3-variable function using the Shannon expansion on the data inputs.