8 to 1 Multiplexer

In short: An 8-to-1 multiplexer uses three select lines (S2 S1 S0) to steer exactly one of eight data inputs to a single output, and in Verilog you can model it with a case statement, an indexed vector, nested conditional operators or a structural tree of 2-to-1 muxes, all of which synthesise to essentially the same hardware.

What an 8-to-1 multiplexer does

A multiplexer (mux) is a digitally controlled switch. The 8-to-1 version has eight data inputs, I0 to I7, one output Y, and a binary select word of log2(8) = 3 bits. Whatever number the select word spells out, that input is connected to Y; the other seven are ignored. If you have already worked through the smaller sibling, our 4-to-1 multiplexer guide, think of this one as the same idea with one more select bit and twice the fan-in.

Muxes are everywhere: register-file read ports, ALU result selection, bus arbitration, serialisers, and the lookup tables inside FPGAs. A 3-input LUT is literally an 8-to-1 mux whose data inputs are the stored configuration bits, and the LUT inputs drive the select lines.

Truth table and Boolean equation

Because there are 11 inputs in total, a full truth table would need 2,048 rows. Engineers therefore write the compact, function-table form, using the data inputs as symbols:

Each row is a minterm of the select lines ANDed with its data input, and the output is the OR of all eight products:

Y = S2'S1'S0'·I0 + S2'S1'S0·I1 + S2'S1S0'·I2 + S2'S1S0·I3 + S2S1'S0'·I4 + S2S1'S0·I5 + S2S1S0'·I6 + S2S1S0·I7

Key fact: the select lines form a one-hot decoder. A 3-to-8 decoder generates the eight minterms, each minterm enables one AND gate, and an 8-input OR collects the result.

Gate-level implementation and cost

The direct two-level implementation needs three inverters, eight 4-input AND gates and one 8-input OR gate. Since standard cells rarely offer an 8-input OR, a synthesis tool such as Synopsys Design Compiler or Cadence Genus will split it into NOR4 plus NAND2 stages. In a typical standard-cell library, a hand-tuned mux2 cell is smaller and faster than the AND-OR equivalent, so mapping often picks a mux tree instead.

That tree is the second classic structure. Four 2-to-1 muxes in the first rank are driven by S0, two in the second by S1, and one in the final rank by S2. That is 7 mux2 cells in total, and the critical path crosses three of them.

Key fact: an N-to-1 mux always needs N-1 two-input muxes in a tree. For N = 8 that is 7, for N = 4 it is 3, which is why the structure scales cleanly.

Verilog modelling styles

All four styles below describe the same function. Pick the one that reads best for your team; the synthesiser will optimise each into a similar netlist.

1. Behavioural case statement. The most readable form, and the one interviewers expect first.

module mux8_case (
  input  [7:0] i,
  input  [2:0] s,
  output reg   y
);
  always @(*) begin
    case (s)
      3'd0: y = i[0];
      3'd1: y = i[1];
      3'd2: y = i[2];
      3'd3: y = i[3];
      3'd4: y = i[4];
      3'd5: y = i[5];
      3'd6: y = i[6];
      3'd7: y = i[7];
      default: y = 1'bx;
    endcase
  end
endmodule

2. Indexed vector select. The shortest form: assign y = i[s];. Treat the data inputs as a bus and let the select word index it. It is compact, synthesisable, and scales to any width by changing a parameter.

3. Conditional operator chain. assign y = s[2] ? (s[1] ? (s[0] ? i[7] : i[6]) : (s[0] ? i[5] : i[4])) : (s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0])); This literally spells out the tree from the figure above.

4. Structural. Instantiate seven copies of a mux2 module and wire them as in the diagram. This is how you would hand-craft a datapath or reproduce a netlist.

mux2 m0(.a(i[0]), .b(i[1]), .s(s[0]), .y(w0));
mux2 m1(.a(i[2]), .b(i[3]), .s(s[0]), .y(w1));
mux2 m2(.a(i[4]), .b(i[5]), .s(s[0]), .y(w2));
mux2 m3(.a(i[6]), .b(i[7]), .s(s[0]), .y(w3));
mux2 m4(.a(w0),  .b(w1),  .s(s[1]), .y(w4));
mux2 m5(.a(w2),  .b(w3),  .s(s[1]), .y(w5));
mux2 m6(.a(w4),  .b(w5),  .s(s[2]), .y(y));

Pitfalls interviewers probe

• Latches: if a case statement omits the default and some branch does not assign y, synthesis infers a latch. Always assign y on every path.
• Sensitivity list: use always @(*) (or always_comb in SystemVerilog) so you never forget a signal.
• X propagation: in simulation, a select of X makes i[s] return X, but a case statement with a default may hide it. Be deliberate about which behaviour you want.

Watching the select word move

The animation below counts the select word from 000 to 111. The highlighted bar marks the input currently routed to Y.

Timing, power and real-world use

In a mux tree, delay grows with log2(N) stages, so three mux2 delays for N = 8. In a 28 nm library a mux2 may take roughly 40 to 60 ps, giving about 150 ps for the full tree before wire load. The decoded AND-OR version has fewer logic levels but needs the select lines to fan out to eight gates, so buffering matters. Static timing tools such as Synopsys PrimeTime or Cadence Tempus will report the worst select-to-output arc, which is usually S0 in a tree because it drives the most cells (four).

In custom CMOS, designers favour transmission-gate muxes: a pass-gate tree uses 14 transmission gates (28 transistors) plus select inverters, and charge-sharing and glitch behaviour must be checked in SPICE. On FPGAs, the mux is absorbed into LUT and carry fabric, so a Xilinx 7-series slice can build an 8-to-1 mux from a pair of LUT6s and the F7 mux without any extra logic.

One favourite interview trick: implement any 4-variable function with a single 8-to-1 mux. Feed three variables to the selects and tie each data input to 0, 1, the fourth variable D, or D'. For example, F(A,B,C,D) = sum of minterms (1, 5, 6, 7, 9, 11, 12, 13, 14) needs only those four constants per pair of rows. This is Shannon expansion in hardware.

Key fact: with n select lines, a 2^n-to-1 mux implements any (n+1)-input Boolean function by tying data inputs to 0, 1, the last variable or its complement.

Where to go from here

Try extending the Verilog above to a parameterised width, then simulate it with a self-checking testbench in Siemens Questa, Synopsys VCS or Cadence Xcelium. Next, compare it with the inverse operation in our 3-to-8 decoder article, and see how the full set of topics fits together on the CourseTron courses page. If you want hands-on RTL and verification training aimed at placements, the team at ChipXpert VLSI training runs instructor-led batches.

Ready to design real digital circuits? Join the CourseTron Digital Electronics course and practise muxes, decoders and Verilog with guided labs.

Frequently asked questions

How many select lines does an 8-to-1 multiplexer need?

Three. The number of select lines is log2 of the number of inputs, and log2(8) = 3.

How many 2-to-1 muxes make an 8-to-1 mux?

Seven: four in the first rank, two in the second and one in the last, arranged as a binary tree.

Which Verilog style is best for synthesis?

All four are synthesisable and typically map to similar logic. The case statement or the indexed form is preferred for readability, provided every path assigns the output so no latch is inferred.

Can a multiplexer implement logic functions?

Yes. A 2^n-to-1 mux can implement any function of n+1 variables, which is exactly how FPGA lookup tables work.