Multiplexer vs Demultiplexer

In short: A multiplexer (MUX) funnels many data inputs onto one output, picking the winner with n select lines, while a demultiplexer (DEMUX) does the exact reverse by steering one input onto one of many outputs using the same kind of select code.

The one-line mental model

Think of a railway junction. A multiplexer is a many-to-one merge: several tracks arrive, a signalman (the select code) lets exactly one through onto the single outgoing line. A demultiplexer is the mirror image: one track arrives and the signalman fans it out to exactly one of several destinations. Both blocks are purely combinational, both are driven by select lines, and both scale by powers of two. The confusion in interviews usually comes from the fact that the pin counts look symmetrical, so let us be precise.

For a 2ⁿ:1 MUX you have 2ⁿ data inputs, n select lines and 1 output. For a 1:2ⁿ DEMUX you have 1 data input, n select lines and 2ⁿ outputs. A 4:1 MUX therefore needs 2 select lines, an 8:1 MUX needs 3, and a 16:1 MUX needs 4. If you have already read our primer on the multiplexer, this article focuses on the contrast.

Inputs, outputs and select lines side by side

Key fact: Select lines grow logarithmically, not linearly. Going from 4 to 64 channels only takes the select bus from 2 bits to 6 bits, which is why muxing is the standard way to save pins and routing.

How each one is built from gates

A 4:1 MUX is an AND-OR structure. Each input is ANDed with a decoded select minterm, then four product terms are ORed. In other words, the MUX contains a small decoder internally. A 1:4 DEMUX is the same decoder, except each AND gate also receives the data input D instead of feeding a shared OR. That is why a decoder with an enable pin is functionally a demultiplexer: tie the enable to your data and you have a DEMUX. The classic 74HC138 (3-to-8 decoder) is routinely sold and used as a 1:8 DEMUX, and the 74HC139 as a dual 1:4 DEMUX. On the MUX side, the 74HC151 is an 8:1, the 74HC153 a dual 4:1 and the 74HC157 a quad 2:1.

Watch the data move

The animation below cycles the select code through 00, 01, 10 and 11. Notice how, in the multiplexer, the selected input lane lights up and travels to Y; in the demultiplexer, the single input D fans out to whichever output the code points at.

Where each block earns its keep

Multiplexer use cases

• Data selection and pin saving. A microcontroller with 8 analog channels shares one ADC through an analog MUX such as the 74HC4051, using 3 select pins instead of 8 converters.
• Parallel-to-serial conversion. Counting the select lines through 000 to 111 serialises an 8-bit word onto a single wire.
• Universal logic. A 2ⁿ:1 MUX can realise any Boolean function of n+1 variables: feed n variables to the select lines and wire each data input to 0, 1, the last variable or its complement. A 4:1 MUX implements any 3-input function, and FPGA LUTs are essentially trees of such muxes.
• Datapath steering. Choosing between ALU result, load data and forwarded operand in a CPU pipeline is a MUX per register-file port.

Demultiplexer use cases

• Address decoding. Chip-select generation from upper address bits, for example a 3-to-8 decode turning A15:A13 into eight memory-bank selects.
• Serial-to-parallel distribution. A time-division link delivers each time slot to its own channel buffer.
• Write-enable steering. A register file uses a decoder to assert exactly one register's load-enable for a write port.
• Clock-gate or interrupt routing where one control signal must reach a single chosen target.

In a real link, a MUX at the transmitter and a DEMUX at the receiver, driven by synchronised select counters, form the heart of time-division multiplexing: one wire carries four channels, and the matched pair restores them.

Interview favourite: "Is a decoder the same as a demux?" Almost. A decoder has n inputs and 2ⁿ outputs with one active; a demux is a decoder whose enable carries the data. Wire D to the enable and the equivalence is exact.

RTL and implementation notes

In SystemVerilog both are one-liners, which is exactly why they hide bugs when select widths are wrong.

// 4:1 MUX
assign y = in[sel];            // in is logic [3:0], sel is logic [1:0]

// 1:4 DEMUX
always_comb begin
  out      = '0;               // default prevents inferred latches
  out[sel] = d;
end

The default assignment in the DEMUX is critical: without it a synthesis tool infers a latch on the unselected outputs, and lint tools flag it. Logic synthesis in Synopsys Design Compiler or Cadence Genus will usually map the MUX onto a library MUX2/MUX4 cell if one exists, or onto AOI22 plus NAND structures otherwise; MUX cells are often smaller than the equivalent gates but have a slower select-to-output arc. Simulation in Siemens Questa or Synopsys VCS should include a test that sweeps every select value and checks all outputs, since a DEMUX bug is typically a leaked non-selected output rather than a wrong selected one.

A subtle hardware issue is the static-1 hazard. In a 2:1 MUX Y = S'A + SB, if A = B = 1 and S switches, the output can briefly glitch low because one AND term turns off before the other turns on. Adding the consensus term AB removes it. For clock selection, never glitch-prone MUX the clock directly; use a glitch-free clock-switch cell with handshaked select, a topic covered in static-timing and CDC reviews.

Common mistakes to avoid

• Counting select lines as the number of inputs. It is log₂, not the count.
• Forgetting that a DEMUX output not selected is idle, not high-impedance, unless you add tri-state buffers.
• Cascading muxes without checking delay: a 16:1 MUX built from five 4:1 stages has two levels, so budget two select-to-output arcs in timing.
• Using an analog switch MUX (CD4051) where you need digital isolation; it passes analog voltages and is bidirectional, so the same part acts as MUX or DEMUX.

If you want hands-on practice building these blocks, simulating them and synthesising them to gates, our structured digital design courses walk through them end to end. Related reading: decoder versus encoder. For industry-level training in RTL and verification, see ChipXpert's VLSI training programmes.

Ready to go beyond block diagrams? Enrol in the CourseTron Digital Electronics course and build, simulate and synthesise MUX and DEMUX circuits yourself. Browse courses.

Frequently asked questions

Can I use a multiplexer as a demultiplexer?

Not a digital one, in general. A logic MUX is unidirectional. However, analog-switch devices like the 4051 are bidirectional and work either way, and a decoder with enable serves as a digital DEMUX.

How many select lines does a 16:1 MUX need?

Four, since 2⁴ = 16. Likewise a 1:32 DEMUX needs five.

Why is a MUX called a universal logic element?

Because a 2ⁿ:1 MUX can implement any function of n+1 variables by tying data inputs to constants or the remaining variable, which is how FPGA lookup tables work.

What is the difference between a demultiplexer and a decoder?

A decoder has n coded inputs and 2ⁿ one-hot outputs. A DEMUX adds a data input that is routed to the selected output. A decoder with an enable pin acts as a DEMUX.